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NUC100-VD2N Fiches technique(PDF) 49 Page - Nuvoton Technology Corporation |
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NUC100-VD2N Fiches technique(HTML) 49 Page - Nuvoton Technology Corporation |
49 / 89 page NuMicro ™ NUC120 Data Sheet Publication Release Date: Jan. 2, 2012 - 49 - Revision V2.03 5.11.2 Features 18-bit free running counter to avoid chip from Watchdog timer reset before the delay time expires. Selectable time-out interval (2 4 ~ 218) and the time out interval is 104 ms ~ 26.3168 s (if WDT_CLK = 10 kHz). Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz. 5.12 UART Interface Controller (UART) NuMicro ™ NUC100/NUC120 Medium Density provides up to three channels of Universal Asynchronous Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform Normal Speed UART, besides, only UART0 and UART1 support flow control function. NuMicro ™ NUC100/NUC120 Low Density only supports UART0 and UART1. 5.12.1 Overview The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also supports IrDA SIR Function and RS-485 mode functions. Each UART channel supports seven types of interrupts including transmitter FIFO empty interrupt (INT_THRE), receiver threshold level reaching interrupt (INT_RDA), line status interrupt (parity error or framing error or break interrupt) (INT_RLS), receiver buffer time out interrupt (INT_TOUT), MODEM/Wake-up status interrupt (INT_MODEM) and Buffer error interrupt (INT_BUF_ERR). Inte umber 12 (vector number is 28); Interrupt number 13 (vector number is 29) only supports UART1 interrupt. Refer to Nested Vectored Interrupt Controller chapter for System Interrupt Map. The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU and the UART1~2 are equipped 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU can read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur while receiving data. The UART includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and BRD are defined in Baud Rate Divider Register (UA_BAUD). Table 5-6 lists the equations in the various conditions and Table 5-7 list the UART baud rate setting table. rrupts of UART0 and UART2 share the interrupt n Mode DIV_X_EN DIV_X_ONE Divider X BRD Baud rate equation 0 0 0 B A UART_CLK / [16 * (A+2)] 1 1 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8 2 1 1 Don’t care A UART_CLK / (A+2), A must >=3 Table 5-6 UART Baud Rate Equation |
Numéro de pièce similaire - NUC100-VD2N |
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Description similaire - NUC100-VD2N |
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