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NUC140-LE2E Fiches technique(PDF) 11 Page - Nuvoton Technology Corporation |
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NUC140-LE2E Fiches technique(HTML) 11 Page - Nuvoton Technology Corporation |
11 / 97 page NuMicro NUC230/240 Datasheet Dec. 30, 2014 Page 11 of 97 Revision 1.01 SPI – Up to four sets of SPI controllers – The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V) – The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V) – Supports SPI Master/Slave mode – Full duplex synchronous serial data transfer – Variable length of transfer data from 8 to 32 bits – MSB or LSB first data transfer – Rx and Tx on both rising or falling edge of serial clock independently – Two slave/device select lines in Master mode, and one slave/device select line in Slave mode – Supports Byte Suspend mode in 32-bit transmission – Supports PDMA mode – Supports three wire, no slave select signal, bi-direction interface I 2C – Up to two sets of I 2C devices – Master/Slave mode – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial data on the bus – Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus – Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer – Programmable clocks allowing for versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports wake-up function I 2S – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I 2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving PS/2 Device – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus CAN 2.0 – Supports CAN protocol version 2.0 part A and B – Bit rates up to 1M bit/s – 32 Message Objects – Each Message Object has its own identifier mask – Programmable FIFO mode (concatenation of Message Object) – Maskable interrupt – Disabled Automatic Re-transmission mode for Time Triggered CAN applications – Support wake-up function ADC – 12-bit SAR ADC with 1 MSPS (chip working at 5V) – Up to 8-ch single-end input or 4-ch differential input – Single scan/single cycle scan/continuous scan |
Numéro de pièce similaire - NUC140-LE2E |
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Description similaire - NUC140-LE2E |
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