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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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N681387DG Fiches technique(PDF) 34 Page - Nuvoton Technology Corporation |
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N681387DG Fiches technique(HTML) 34 Page - Nuvoton Technology Corporation |
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34 / 164 page  N681386/87 Single Programmable Extended Codec/SLCC Preliminary Datasheet Rev1.0 Page 34 of 164 January 2010 Register Bit(s) Address Parameter Programmable Range APG PALT[7:0] 0x9F Power Alarm Counter Increment on every rising edge of LOW VDC or HIGH IDC; clip at 255; Table 11: PWM DC/DC Power Alarm Counter 12.1.2.1. THERMAL OVERLOAD In addition to voltage and current monitoring described in section 6.1.1.1 “Linefeed States of Operation”, N681386/87 continuously monitors the power dissipation of each external transistor in the Linefeed circuitry. After Low Pass Filtering, the power dissipation is compared against thresholds which are listed in Table 10. The threshold and the Low Pass Filter pole are both programmable and should be set according to the characteristics of the individual transistor as follows. The Low Pass Filter pole for QT1 and QR1 is given by the equation: 13 TC 2 T 800 1 1 ] 0 : 12 [ C 1 Q × ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ × − = Where TTC is the thermal time constant of the external transistor. The threshold should be programmed according to the maximum power dissipation of the external transistor. If the threshold is exceeded a power alarm event is deemed to have occurred. An associated interrupt may be enabled. An automatic state transition into Open state may be enabled by setting Power Alarm Automatic React (LAMC:PAA[2]) address (0x43)). Register Bit(s) Address Parameter Description / Range PALPQ1 PALPQH1 PALPQH2 Q1C[7:0] Q1C[11:8] Q1C[12] 0xA1 0xA3 0xA4 PA Low Pass Filter Pole for QT1 and QR1 See Register Description PALPQ2 PALPQH1 PALPQH2 Q2C[7:0] Q2C[11:8] Q2C[12] 0xA0 0xA3 0xA4 PA Low Pass Filter Pole for QT2 and QR2 See Register Description PALPQ3 PALPQH2 PALPQH2 Q2C[7:0] Q3C[11:8] Q3C[12] 0xA2 0xA3 0xA4 PA Low Pass Filter Pole for QT3 and QR3 See Register Description PATHQ1 Q1TH[7:0] 0xA6 PA Threshold for QT1 and QR1 0 to 7.7 W in 30.4 mW steps PATHQ2 Q2TH[7:0] 0xA5 PA Threshold for QT2 and QR2 0 to 0.97 W in 3.8 mW steps PATHQ3 Q3TH[7:0] 0xA7 PA Threshold for QT3 and QR3 0 to 7.7 W in 30.4 mW steps INT1 0x26 Power Alarm Interrupt Enable/Disable IE1 0x27 Power Alarm Interrupt Enable Enable/Disable LAMC PAA[2] 0x43 Power Alarm Automatic React Enable/Disable Table 12: Registers Associated with Thermal Overload |
Numéro de pièce similaire - N681387DG |
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Description similaire - N681387DG |
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