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MC7445 Fiches technique(PDF) 10 Page - Freescale Semiconductor, Inc

No de pièce MC7445
Description  RISC Microprocessor Hardware Specifications
Download  64 Pages
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC7445 Fiches technique(HTML) 10 Page - Freescale Semiconductor, Inc

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
10
Freescale Semiconductor
Electrical and Thermal Characteristics
5
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7455.
5.1 DC Electrical Characteristics
The tables in this section describe the MPC7455 DC electrical characteristics. Table 2 provides the absolute
maximum ratings.
Table 2. Absolute Maximum Ratings 1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.95
V
4
PLL supply voltage
AVDD
–0.3 to 1.95
V
4
Processor bus supply voltage
BVSEL = 0
OVDD
–0.3 to 1.95
V
3, 6
BVSEL = HRESET or OVDD
OVDD
–0.3 to 2.7
V
3, 7
L3 bus supply voltage
L3VSEL = ¬HRESET
GVDD
–0.3 to 1.65
V
3, 8
L3VSEL = 0
GVDD
–0.3 to 1.95
V
3, 9
L3VSEL = HRESET or GVDD
GVDD
–0.3 to 2.7
V
3, 10
Input voltage
Processor bus
Vin
–0.3 to OVDD + 0.3
V
2, 5
L3 bus
Vin
–0.3 to GVDD + 0.3
V
2, 5
JTAG signals
Vin
–0.3 to OVDD + 0.3
V
Input voltage
Processor bus
Vin
–0.3 to OVDD + 0.3
V
2, 5
JTAG signals
Vin
–0.3 to OVDD + 0.3
V
Storage temperature range
Tstg
–55 to 150
°C
Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. Caution: Vin must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. BVSEL must be set to 0, such that the bus is in 1.8 V mode.
7. BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
8. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5 V mode.
9. L3VSEL must be set to 0, such that the bus is in 1.8 V mode.
10.L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.


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