TPS51020

SLUS564B − JULY 2003 − REVISED DECEMBER 2003

3

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INV1

COMP1

SSTRT1

SKIP

VO1_VDDQ

DDR

GND

REF_X

ENBL1

ENBL2

VO2

PGOOD

SSTRT2

COMP2

INV2

VBST1

OUT1_U

LL1

OUT1_D

OUTGND1

TRIP1

VIN

TRIP2

VREG5

REG5_IN

OUTGND2

OUT2_D

LL2

OUT2_U

VBST2

TSSOP (0.5 mm)

DBT PACKAGE

(TOP VIEW)

ELECTRICAL CHARACTERISTICS

TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,

INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =

OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENTS

IVIN

VIN supply current

REG5V_IN = OPEN,

TRIPx = VIN,

OSC = OFF

1.4

2.2

mA

IVIN(STBY)

VIN standby current

ENBLx = 0 V,

DDR = VIN,

REG5V_IN = OPEN,

OSC = OFF

350

550

IVIN(SHDN)

VIN shutdown current

ENBLx = DDR = 0 V,

REG5V_IN = OPEN

0.05

1.00

µA

IVIN(REG5)

VIN supply current, REG5_IN as 5-V input

current

REG5V_IN = 5 V,

OSC = OFF

200

500

IREG5

REG5_IN input supply current

REG5V_IN = 5 V,

OSC = OFF

1.0

1.7

mA

IVBSTx

VBST supply current

ENBLx = DDR = VIN

0.05

1.00

A

IVBSTx

VBST shutdown current

ENBLx = DDR = 0 V

0.05

1.00

µA

VREG5 INTERNAL REGULATOR

VVREG5

VREG5 voltage

IOUT = 0 A

4.8

5.0

5.2

V

VLD5

Load regulation

0 mA

≤ IOUT ≤ 50 mA,

VIN = 12 V

0.6%

2.5%

VLN5

Line regulation

IOUT = 20 mA,

7 V

≤VIN ≤ 28 V

0.4%

2.0%

VTHL

UVLO threshold voltage

High to low

3.45

3.65

3.85

V

VHYS(UV)

UVLO hysteresis

100

200

300

mV

VTH(SW)

Switchover voltage

REG_IN voltage

4.2

4.5

4.8

V

VHYS(SW)

Switchover hysteresis

50

250

mV