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AD9958BCPZ-REEL7 Fiches technique(PDF) 10 Page - Analog Devices |
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AD9958BCPZ-REEL7 Fiches technique(HTML) 10 Page - Analog Devices |
10 / 40 page AD9958 Rev. 0 | Page 10 of 40 Pin No. Mnemonic I/O Description 24 CLK_MODE_SEL I Control Pin for the Oscillator Section. CAUTION: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator section is enabled to accept a crystal as the REF_CLK source. When low, the oscillator section is bypassed. 27 LOOP_FILTER I Connects to the external zero compensation network of the PLL loop filter. Typically the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD. 28, 32, 34, 38 NC - No Connection. 40, 41,42,43 P0, P1, P2, P3 I Data pins used for modulation (FSK, PSK, ASK), start/stop for the sweep accumulators or are used to ramp up/down the output amplitude. Note the SYNC_CLK must be enabled in these modes. Any toggle of these data inputs is equivalent to an I/O_UPDATE. The data is synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the set-up and hold time requirements to the SYNC_CLK. This guarantees a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of uncertainty exists. The functionality of these pins is controlled by profile pin configuration (PPC) bits in Register FR1 <12:14>. 46 I/O_UPDATE I A rising edge transfers data from the serial I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the set-up and hold time requirements to the. SYNC_CLK to guarantee a fixed pipeline delay of data to DAC output. If not, a ±1 SYNC_CLK period of uncertainty exists. The minimum pulse width is one SYNC_CLK period. 47 CS I Active low chip select allowing multiple devices to share a common I/O bus (SPI). 48 SCLK I Serial Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK. 49 DVDD_I/O I 3.3 V Digital Power Supply for SPI Port and Digital I/O. 50 SDIO_0, I/O Data Pin SDIO_0 is dedicated to the Serial Port I/O only. 51 52, 53 SDIO_1 SDIO_2, SDIO_3 I/O Data Pins SDIO_1:3 can be used for the serial port I/O port or used to initiate a ramp up/down (RU/RD) of the DAC output amplitude. 54 SYNC_CLK O The SYNC_CLK runs at one fourth the system clock rate. It can be disabled. I/O_UPDATE or data (Pins 40 to 43) is synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE or data (Pins 40 to 43) must meet the set-up and hold time requirements to the rising edge of SYNC_CLK. If not, a ±1 SYNC_CLK period of uncertainty exists. |
Numéro de pièce similaire - AD9958BCPZ-REEL7 |
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Description similaire - AD9958BCPZ-REEL7 |
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