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HCPL-2630 Fiches technique(PDF) 1 Page - Fairchild Semiconductor

No de pièce HCPL-2630
Description  HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
Download  12 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

HCPL-2630 Fiches technique(HTML) 1 Page - Fairchild Semiconductor

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©2005 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
July 2005
Single-channel: 6N137, HCPL-2601, HCPL-2611 Dual-Channel: HCPL-2630, HCPL-2631 Rev. 1.0.3
Single-channel: 6N137, HCPL-2601, HCPL-2611
Dual-Channel: HCPL-2630, HCPL-2631
High Speed-10 MBit/s Logic Gate Optocouplers
Features
Very high speed-10 MBit/s
Superior CMR-10 kV/µs
Double working voltage-480V
Fan-out of 8 over -40°C to +85°C
Logic gate output
Strobable output
Wired OR-open collector
U.L. recognized (File # E90700)
Applications
■ Ground loop elimination
■ LSTTL to TTL, LSTTL or 5-volt CMOS
■ Line receiver, data transmission
■ Data multiplexing
■ Switching power supplies
■ Pulse transformer replacement
■ Computer-peripheral interface
Description
The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/
2631 dual-channel optocouplers consist of a 850 nm AlGaAS
LED, optically coupled to a very high speed integrated photo-
detector logic gate with a strobable output. This output features
an open collector, thereby permitting wired OR outputs. The
coupled parameters are guaranteed over the temperature range
of -40°C to +85°C. A maximum input signal of 5 mA will provide
a minimum output sink current of 13mA (fan out of 8).
An internal noise shield provides superior common mode rejec-
tion of typically 10kV/µs. The HCPL- 2601 and HCPL- 2631 has
a minimum CMR of 5 kV/µs. The HCPL-2611 has a minimum
CMR of 10 kV/µs.
PackageSchematic
Truth Table (Positive Logic)
A 0.1µF bypass capacitor must be connected between pins 8 and 5. (See note 1)
8
8
1
8
1
1
1
2
3
4
5
6
7
8
N/C
_
V
CC
V
E
V
O
GND
+
N/C
V
F
1
2
3
4
5
6
7
8
+
_
V
F1
V
CC
V
01
V
02
GND
V
F2
_
+
HCPL-2630
HCPL-2631
6N137
HCPL-2601
HCPL-2611
Input
Enable
Output
H
H
L
L
H
H
H
L
H
L
L
H
H
NC
L
L
NC
H


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