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74HC3G34DC Fiches technique(PDF) 10 Page - NXP Semiconductors |
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74HC3G34DC Fiches technique(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 2003 May 19 10 Philips Semiconductors Product specification Triple buffer gate 74HC3G34; 74HCT3G34 AC WAVEFORMS handbook, halfpage MNA746 tPLH tPHL VM VM 90% 10% VM VM nY output nA input VI GND VOH VOL tTLH tTHL Fig.4 The input (nA) to output (nY) propagation delays and the output transition times. For 74HC3G: VM = 50%; VI = GND to VCC. For 74HCT3G: VM = 1.3 V; VI = GND to 3.0 V. handbook, full pagewidth open GND 50 pF VCC VCC VI VO MNA742 D.U.T. CL = RT RL = 1 k Ω PULSE GENERATOR S1 Fig.5 Load circuitry for switching times. Definitions for test circuit: RL = Load resistor. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND |
Numéro de pièce similaire - 74HC3G34DC |
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Description similaire - 74HC3G34DC |
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