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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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P87LPC759 Fiches technique(PDF) 29 Page - NXP Semiconductors |
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P87LPC759 Fiches technique(HTML) 29 Page - NXP Semiconductors |
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29 / 38 page  Philips Semiconductors Preliminary data P87LPC759 Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP 2002 Mar 21 27 EPROM Characteristics Programming of the EPROM on the P87LPC759 is accomplished with a serial programming method. Commands, addresses, and data are transmitted to and from the device on two pins after programming mode is entered. Serial programming allows easy implementation of On-Board Programming of the P87LPC759 in an application board. Details of On-Board Programming can be found in application note AN466. The P87LPC759 contains three signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes designate the device as an P87LPC759 manufactured by Philips. The signature bytes may be read by the user program at addresses FC30h, FC31h and FC60h with the MOVC instruction, using the DPTR register for addressing. System Configuration Bytes A number of user configurable features of the P87LPC759 must be defined at power up and therefore cannot be set by the program after start of execution. Those features are configured through the use of two EPROM bytes that are programmed in the same manner as the EPROM program space. The contents of the two configuration bytes, UCFG1 and UCFG2, are shown in Figures 27 and 28. The values of these bytes may be read by the program through the use of the MOVX instruction at the addresses shown in the figure. BIT SYMBOL FUNCTION UCFG1.7 WDTE Watchdog timer enable. When programmed (0), disables the watchdog timer. The timer may still be used to generate an interrupt. UCFG1.6 RPD Reset pin disable. When 1 disables the reset function of pin P1.5, allowing it to be used as an input only port pin. UCFG1.5 PRHI Port reset high. When 1, ports reset to a high state. When 0, ports reset to a low state. UCFG1.4 BOV Brownout voltage select. When 1, the brownout detect voltage is 2.5V. When 0, the brownout detect voltage is 3.8V. This is described in the Power Monitoring Functions section. UCFG1.3 CLKR Clock rate select. When 0, the CPU clock rate is divided by 2. This results in machine cycles taking 12 CPU clocks to complete as in the standard 80C51. For full backward compatibility, this division applies to peripheral timing as well. UCFG1.2–0 FOSC2–FSOC0 CPU oscillator type select. See Oscillator section for additional information. Combinations other than those shown below should not be used. They are reserved for future use. FOSC2–FOSC0 Oscillator Configuration 1 1 1 External clock input on X1 (default setting for an unprogrammed part). 0 1 1 Internal RC oscillator, 6 MHz. For tolerance, see AC Electrical Characteristics table. 0 1 0 Low frequency crystal, 20 kHz to 100 kHz. 0 0 1 Medium frequency crystal or resonator, 100 kHz to 4 MHz. 0 0 0 High frequency crystal or resonator, 4 MHz to 20 MHz. FOSC0 SU01477 FOSC1 FOSC2 CLKR BOV PRHI RPD WDTE 0 1 2 3 4 5 6 7 UCFG1 Unprogrammed Value: FFh Address: FD00h Figure 27. EPROM System Configuration Byte 1 (UCFG1) BIT SYMBOL FUNCTION UCFG2.7, 6 SB2, SB1 EPROM security bits. See table entitled, “EPROM Security Bits” for details. UCFG2.5–0 — Reserved for future use. — SU01186 — — — — — SB1 SB2 0 1 2 3 4 5 6 7 UCFG2 Unprogrammed Value: FFh Address: FD01h Figure 28. EPROM System Configuration Byte 2 (UCFG2) |
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Description similaire - P87LPC759 |
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