NB3H73113G datasheet(3/24 Pages) ONSEMI

No de pièce	NB3H73113G

Description	Programmable OmniClock Generator

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NB3H73113G

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Table 1. PIN DESCRIPTION

Pin No.

Pin Name

Pin Type

Description

1

XIN/CLKIN

Input

3 MHz to 50 MHz crystal input connection or an external single ended reference

input clock between 3 MHz and 200 MHz.

2

XOUT

Output

Crystal output. Float this pin when external reference clock is connected at XIN.

3

PD#

Input

Asynchronous LVCMOS/LVTTL input. Active Low Master Reset to disable the

device and set outputs Low. Internal pull−down resistor. This pin needs to be pulled

High for normal operation of the chip.

4

GND

Ground

Power supply ground.

5, 6, 7

OE[2:0]

Input

2−Level LVCMOS/LVTTL Inputs for Enabling/Disabling output clocks CLK[2:0]

respectively. Internal pull−up resistor.

8

VDDO0

Power

CLK0 Output power supply

≤ VDD

9

CLK0

SE/DIFF Output

Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also

be a copy of the input clock. The single ended output will be LOW and differential

outputs will be complementary LOW/HIGH until the PLL has locked and the

frequency has stabilized.

10

CLK1

SE/DIFF Output

Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also

be a copy of the input clock. The single ended output will be LOW and differential

outputs will be complementary LOW/HIGH until the PLL has locked and the

frequency has stabilized.

11

VDDO1

Power

CLK1 Output power supply

≤ VDD

12

VDD

Power

3.3V / 2.5V power supply.

13

CLK2

SE Output

Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals. Using PLL

Bypass mode, the output can also be a copy of the input clock. The single ended

output will be LOW until the PLL has locked and the frequency has stabilized.

14

VDDO2

Power

CLK2 Output power supply

≤ VDD

15

SDATA

Input / Output

I2C / SMBus Interface Signal SDATA

16

SCLK

Input

I2C / SMBus Interface Signal SCLK

EPAD

GNDO

Ground

Power supply ground for Outputs.

Table 2. POWER DOWN FUNCTION TABLE

PD#

Function

0

Device Powered Down

1

Device Powered Up

Table 3. OUTPUT ENABLE FUNCTION TABLE

OE[2:0]

Function

0

CLK Disabled

1

CLK Enabled

TYPICAL CRYSTAL PARAMETERS

Crystal: Fundamental Mode Parallel Resonant

Frequency: 3 MHz to 50 MHz

Table 4. MAX CRYSTAL LOAD CAPACITORS

RECOMMENDATION

Crystal Frequency Range

Max Cap Value

3 MHz − 30 MHz

20 pF

30 MHz − 50 MHz

10 pF

Shunt Capacitance (C0): 7 pF (Max)

Equivalent Series Resistance 150

W (Max)

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