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74AHC377 Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74AHC377 Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 20 page 2000 Aug 15 2 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Ideal for addressable register applications • Data enable for address and data synchronization • Eight positive-edge triggered D-type flip-flops • See “273” for master reset version • See “373” for transparent latch version • See “374” for 3-state version • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and from −40 to +125 °C. DESCRIPTION The 74AHC/AHCT377 D-type flip-flops are high-speed silicon-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT377 devices have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT AHC AHCT tPHL/tPLH propagation delay; CP to Qn CL = 15 pF; VCC = 5 V 3.9 4.0 ns fmax maximum clock frequency CL = 15 pF; VCC = 5 V 175 140 MHz CI input capacitance VI =VCC or GND 3.0 3.0 pF CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 20 23 pF |
Numéro de pièce similaire - 74AHC377 |
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Description similaire - 74AHC377 |
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