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SI5364-F-BC Fiches technique(PDF) 11 Page - Silicon Laboratories |
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SI5364-F-BC Fiches technique(HTML) 11 Page - Silicon Laboratories |
11 / 40 page Si5364 Rev. 2.2 11 Jitter Transfer Bandwidth (see Figure 9)FBW BW = 1600 Hz — 1600 — Hz Wander/Jitter Transfer Peaking JP < 1600 Hz — 0.0 0.1 dB Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 00) Jitter Tolerance (see Figure 8) JTOL(PP) f=32 Hz 1000 — —ns f = 320 Hz 100 — —ns f = 3200 Hz 10 — —ns CLKOUT RMS Jitter Generation FEC[1:0] = 00 (1/1 Scaling) JGEN(RMS) 12 kHz to 20 MHz — 0.89 1.2 ps 50 kHz to 80 MHz — 0.3 0.4 ps CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 (255/238, 238/255 Scal- ing) JGEN(RMS) 12 kHz to 20 MHz — 0.81 1.2 ps 50 kHz to 80 MHz — 0.30 0.4 ps CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 (1/1 Scaling) JGEN(PP) 12 kHz to 20 MHz — 5.8 10.0 ps 50 kHz to 80 MHz — 2.9 5.0 ps CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 (255/238, 238/255 Scal- ing) JGEN(PP) 12 kHz to 20 MHz — 7.9 10.0 ps 50 kHz to 80 MHz — 4.6 5.0 ps Jitter Transfer Bandwidth (see Figure 9) FBW BW = 3200 Hz — 3200 —Hz Wander/Jitter Transfer Peaking JP < 3200 Hz — 0.0 0.05 dB Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 11) Jitter Tolerance (see Figure 8) JTOL(PP) f=64 Hz 1000 — —ns f = 640 Hz 100 — —ns f = 6400 Hz 10 — —ns CLKOUT RMS Jitter Generation FEC[1:0] = 00 (1/1 Scaling) JGEN(RMS) 12 kHz to 20 MHz — 1.03 1.4 ps 50 kHz to 80 MHz — 0.38 0.5 ps CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 (255/238, 238/255 scal- ing) JGEN(RMS) 12 kHz to 20 MHz — 1.01 1.4 ps 50 kHz to 80 MHz — 0.45 0.6 ps CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 (1/1 Scaling) JGEN(PP) 12 kHz to 20 MHz — 9.3 12.0 ps 50 kHz to 80 MHz — 2.8 5.5 ps Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ± 5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/ µs unit is used here since the maximum phase transient magnitude for the Si5364 (tPT_MTIE) never reaches one nanosecond. |
Numéro de pièce similaire - SI5364-F-BC |
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Description similaire - SI5364-F-BC |
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