CAT24FC64

3

Doc. No. 1046, Rev. G

Note:

(1) AC measurement conditions:

Input rise and fall times: < 50ns

(2) This parameter is tested initially and after a design or process change that affects the parameter.

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain

high, and the device does not respond to its slave

address.

A.C. CHARACTERISTICS

Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol

Parameter

Min

Typ

Max

Units

Power-Up to Read Operation

100

µs

Power-Up to Write Operation

100

µs

l

o

b

m

y

Sr

e

t

e

m

a

r

a

PV

5

.

5

-

V

8

.

1

=

C

C

VV

5

.

5

-

V

5

.

2

=

C

C

V

n

i

Mx

a

Mn

i

Mx

a

Ms

t

i

n

U

F

L

C

S

y

c

n

e

u

q

e

r

F

k

c

o

l

C0

0

40

0

0

1z

H

k

t

A

A

d

n

a

t

u

O

a

t

a

D

A

D

S

o

t

w

o

L

L

C

S

t

u

O

K

C

A

5

0

.

09

.

05

0

.

05

.

0s

µ

t

F

U

B

)

2

(

e

r

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f

e

B

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F

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u

M

s

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t

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t

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t

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n

a

C

n

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s

s

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m

s

n

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w

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N

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3

.

15

.

0s

µ

t

A

T

S

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05

2

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16

.

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t

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04

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0s

µ

t

A

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U

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(

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6

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05

2

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0s

µ

t

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A

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10

0

1s

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t

R

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2

(

e

m

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R

L

C

S

d

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S0

23

.

01

.

0s

µ

t

F

)

2

(

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m

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T

ll

a

F

L

C

S

d

n

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S0

20

0

30

0

1s

n

t

O

T

S

:

U

S

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m

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T

p

u

t

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S

n

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t

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d

n

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C

p

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t

S6

.

05

2

.

0s

µ

t

H

D

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m

i

T

d

l

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t

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O

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t

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D0

50

5s

n

t

R

W

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m

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T

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l

c

y

C

e

t

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r

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5

s

m

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C

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,

A

D

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(

n

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p

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I0

50

5s

n

t

P

W

;

U

S

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m

i

T

p

u

t

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S

P

W6

.

05

.

0s

µ

t

P

W

;

D

H

e

m

i

T

d

l

o

H

P

W3

.

18

.

0s

µ