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ISL97686 Fiches technique(PDF) 3 Page - Renesas Technology Corp |
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ISL97686 Fiches technique(HTML) 3 Page - Renesas Technology Corp |
3 / 22 page ISL97686 FN7953 Rev.1.00 Page 3 of 22 Sep 19, 2017 Pin Configurations ISL97686 (28 LD 5x5 TQFN) TOP VIEW ISL97686 (28 LD SOIC) TOP VIEW 1 2 3 4 5 6 7 10 11 12 13 14 15 28 27 26 17 16 19 18 21 20 EN_VSYNC ISET1 COMP OSC VDC VLOGIC OVP ISET2 89 CLK 22 25 24 23 PWM_SET/PLL SDI SDO NC EXPOSED THERMAL PAD CS 1 2 3 4 5 6 7 10 11 12 13 14 15 28 27 26 17 16 19 18 21 20 CH3 CH4 GD PGND SLEW CSEL CH2 CH1 EN_VSYNC NC ISET1 COMP VIN OSC VDC PGND AGND EN VLOGIC OVP ISET2 PGND CS 8 9 CLK 22 25 24 23 PWM_SET/PLL SDI SDO CS Pin Descriptions TQFN SOIC PIN NAME PIN TYPE PIN DESCRIPTION 1 5 SDO I Serial data output to next driver 26 CS IChip select 37 CLK I Serial clock 4 8 SDI I Serial data input 5 9 VLOGIC S Internal 2.5V Digital Bias Regulator. Needs Decoupling Capacitor added to ground 6 10 EN_VSYNC I Frame synchronization enable. Ties high to VDC for enable VSYNC function. PWM_SET/PLL also needs to be configured with an RC network. Pin can be tied to VDC or VLOGIC to enable function 7 11 VDC S Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor added to ground 8 12 VIN S Main Power Input. Range: 9V to 32V 9 13 EN I LED Driver Enable. Whole chip will shut down when low 10 14 AGND S Analog Ground 11 15 GD O External Boost FET gate control 12 16 SLEW I Boost Regulation Switching Slew Rate control 13 17 CS I External Boost FET current sense input 14 18 PGND S Boost FET gate driver power ground and ground reference for CS pin 15 19 PWM_SET/PLL I For direct PWM mode, tie this pin high to VDC. For other non-VSYNC modes, connect to a resistor to set the dimming frequency. If the VSYNC function is enabled, connect this pin to the PLL loop filter network. 16 20 OVP I Overvoltage Protection Input as well as Output Voltage feedback pin 17 21 COMP I Boost compensation 18 22 ISET1 I Resistor connection for setting LED current. 28.7kΩ = 100mA |
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