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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ISL97649B Fiches technique(PDF) 6 Page - Renesas Technology Corp |
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ISL97649B Fiches technique(HTML) 6 Page - Renesas Technology Corp |
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6 / 20 page  ISL97649B FN7927 Rev 2.00 Page 6 of 20 June 27, 2013 DIGITAL CONTROLLED POTENTIOMETER SETVR SET Voltage Resolution (Note 12) 8 Bits SETDNL SET Differential Nonlinearity (Notes 8, 9, 14) TA = +25°C - - ±1 LSB SETZSE SET Zero-Scale Error (Note 10, 14) TA = +25°C - - ±2 LSB SETFSE SET Full-Scale Error (Note 11, 14) TA = +25°C - - ±8 LSB IRSET RSET Current - 100 µA AVDD to SET AVDD to SET Voltage Attenuation - 1:20 - V/V FAULT DETECTION THRESHOLD VUVLO Undervoltage Lock-out Threshold PVIN rising 2.25 2.33 2.41 V PVIN falling 2.125 2.20 2.27 V OVPAVDD Boost Overvoltage Protection Off Threshold to Shut Down IC (Note 13) 15.0 15.5 16.0 V TOFF Thermal Shut-Down all channels Temperature rising 153 °C POWER SEQUENCE TIMING ISS Boost Soft-start Current 3 5.5 8 µA Electrical Specifications VIN = ENABLE = 3.3V, AVDD =8V, VON = 24V, VOFF = -6V. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 7) MAX (Note 6) UNITS Serial Interface Specifications For SCL and SDA, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 14) TYP (Note 7) MAX (Note 14) UNITS fSCL SCL Frequency (Note 6) 400 kHz tiN Pulse Width Suppression Time at SDA and SCL Inputs (Note 6) Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VIN, until SDA exits the 30% to 70% of VIN window. 480 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VIN during the following START condition. 480 ns tLOW Clock LOW Time Measured at 30% of VIN crossing. 480 ns tHIGH Clock HIGH Time Measured at 70% of VIN crossing. 400 ns tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge, both crossing 70% of VIN. 480 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VIN to SCL falling edge crossing 70% of VIN. 400 ns tSU:DAT Input Data Set-up Time From SDA exiting 30% to 70% of VIN window to SCL rising edge crossing 30% of VIN. 40 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VIN to SDA entering 30% to 70% of VIN window. 0ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VIN to SDA rising edge crossing 30% of VIN. 400 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge, both crossing 70% of VIN. 400 ns CSCL Capacitive on SCL 5pF |
Numéro de pièce similaire - ISL97649B |
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Description similaire - ISL97649B |
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