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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ISL6568IRZA Fiches technique(PDF) 24 Page - Renesas Technology Corp |
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ISL6568IRZA Fiches technique(HTML) 24 Page - Renesas Technology Corp |
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24 / 30 page  ISL6568 FN9187 Rev 5.00 Page 24 of 30 Jan 12, 2012 Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately, there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per- channel switching frequency. The values of the compensation components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the following three, there is a separate set of equations for the compensation components. In Equation 29, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and VP-P is the peak-to-peak sawtooth signal amplitude as described in the “Electrical Specifications” on page 6. Once selected, the compensation values in Equations 29 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the value of RC while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from Equations 29 unless some performance issue is noted. The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (See Figure 20). Keep a position available for C2, and be prepared to install a high-frequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted. Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, I, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output-voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount as shown by Equation 30. The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with FIGURE 20. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6568 CIRCUIT ISL6568 COMP CC RC RFB FB VDIFF C2 (OPTIONAL) 1 2 LC ------------------- f0 > RC RFB 2 f 0Vpp LC 0.66VIN ------------------------------------ = CC 0.66VIN 2 V PPRFBf0 ------------------------------------ = Case 1: 1 2 LC ------------------- f0 1 2 C ESR ------------------------------ < RC RFB VPP 2 2 f 0 2 LC 0.66 VIN -------------------------------------------- = CC 0.66VIN 2 2 f 0 2 V PPRFB LC ------------------------------------------------------------- = Case 2: (EQ. 29) f0 1 2 C ESR ------------------------------ > RC RFB 2 f 0VppL 0.66 VIN ESR ------------------------------------------ = CC 0.66VIN ESR C 2 V PPRFBf0 L ------------------------------------------------- = Case 3: V ESL di dt ----- ESR I + (EQ. 30) |
Numéro de pièce similaire - ISL6568IRZA |
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Description similaire - ISL6568IRZA |
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