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ISL51002 Fiches technique(PDF) 7 Page - Renesas Technology Corp

No de pièce ISL51002
Description  10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features
Download  33 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL51002 Fiches technique(HTML) 7 Page - Renesas Technology Corp

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ISL51002
FN6164 Rev 3.00
Page 7 of 33
February 29, 2012
Timing Diagrams
Data Output Setup and Hold Timing
RGB Output Data Timing and Latency
YUV Output Data Timing and Latency
PIXEL DATA
DATACLK
tHOLD
tSETUP
DATACLK
PROGRAMMABLE
WIDTH AND POLARITY
ANALOG
VIDEO IN
P1
P2
P3
P4
P5
P6
P7
P8
P0
P9
D0
R/G/B[9:0]
HSOUT
8 DATACLK PIPELINE LATENCY
P10
P11
P12
D1
D2
D3
HSYNCIN
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED
TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST
OF THE AFE’S OUTPUT SIGNALS
DATACLK
PROGRAMMABLE
WIDTH AND POLARITY
ANALOG
VIDEO IN
P1
P2
P3
P4
P5
P6
P7
P8
P0
P9
HSOUT
8 DATACLK PIPELINE LATENCY
P10
P11
P12
HSYNCIN
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.
THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE
AFE’S OUTPUT SIGNALS
DATACLK
G0 (YO) G1 (Y1)G2 (Y2)
B0 (UO)R0 (V0)B2 (U2)
G[9:0]
R[9:0]
B[9:0]
G3 (Y3)
R2 (V2)


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