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LT1469 Fiches technique(PDF) 8 Page - Linear Technology

No de pièce LT1469
Description  Octal, 16-Bit, 200ksps Differential 짹10.24V Input SoftSpan ADC with Wide Input Common Mode Range
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Fabricant  LINER [Linear Technology]
Site Internet  http://www.linear.com
Logo LINER - Linear Technology

LT1469 Fiches technique(HTML) 8 Page - Linear Technology

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LTC2348-16
8
234816fa
For more information www.linear.com/LTC2348-16
CMOS Timings
0.8 • OVDD
0.2 • OVDD
50%
50%
234816 F01
0.2 • OVDD
0.8 • OVDD
0.2 • OVDD
0.8 • OVDD
tDELAY
tWIDTH
tDELAY
LVDS Timings (Differential)
+200mV
–200mV
0V
0V
234816 F01b
–200mV
+200mV
–200mV
+200mV
tDELAY
tWIDTH
tDELAY
Figure 1. Voltage Levels for Timing Specifications
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: VDDLBYP is the output of an internal voltage regulator, and should
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below VEE or above VCC, they
will be clamped by internal diodes. This product can handle input currents
of up to 100mA below VEE or above VCC without latch-up.
Note 5: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
currents of up to 100mA below ground or above VDD or OVDD without
latch-up.
Note 6: –16.5V ≤ VEE ≤ 0V, 0V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V,
VDD = 5V, unless otherwise specified.
Note 7: Recommended operating conditions.
Note 8: Exceeding these limits on any channel may corrupt conversion
results on other channels. Refer to Absolute Maximum Ratings section for
pin voltage limits related to device reliability.
Note 9: VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 200ksps,
internal reference and buffer, true bipolar input signal drive in bipolar
SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless
otherwise specified.
Note 10: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 11: Guaranteed by design, not subject to test.
Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
the offset voltage measured from –0.5LSB when the output code flickers
between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
error for these SoftSpan ranges is the worst-case deviation of the first and
last code transitions from ideal and includes the effect of offset error. For
unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage
measured from 0.5LSB when the output code flickers between 0000 0000
0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
ranges is the worst-case deviation of the last code transition from ideal
and includes the effect of offset error.
Note 13: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 16: IREFBUF varies proportionally with sample rate and the number of
active channels.
Note 17: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
and OVDD = 5.25V.
Note 18: A tSCKI period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising edge capture.
Note 19: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
aDc TiMing characTerisTics


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