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74VCXH16374 Fiches technique(PDF) 1 Page - STMicroelectronics |
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74VCXH16374 Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 12 page 1/12 February 2003 s 3.6V TOLERANT INPUTS AND OUTPUTS s HIGH SPEED : tPD = 3.0 ns (MAX.) at VCC =3.0 to 3.6V tPD = 3.9 ns (MAX.) at VCC =2.3 to 2.7V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL = 24mA (MIN) at VCC =3.0V |IOH|= IOL = 18mA (MIN) at VCC =2.3V s OPERATING VOLTAGE RANGE: VCC(OPR) = 2.3V to 3.6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES H16374 s BUS HOLD PROVIDED ON DATA INPUTS s LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74VCXH16374 is a low voltage CMOS 16 BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 2.3 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs. These 16 bit D-TYPE flip-flops are controlled by two clock inputs (nCK) and two output enable inputs (nOE). On thepositivetransitionof the (nCK), thenQ outputs will be set to the logic state that were setup at the nD inputs. While the (nOE) input is low, the 8 outputs (nQ) will be in a normal state (HIGH or LOW logic level) and while high level the outputs will be in a high impedance state. Any output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. 74VCXH16374 LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS ORDER CODES PACKAGE TUBE T & R TSSOP 74VCXH16374TTR TSSOP PIN CONNECTION |
Numéro de pièce similaire - 74VCXH16374 |
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Description similaire - 74VCXH16374 |
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