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MP8763D Fiches technique(PDF) 17 Page - Monolithic Power Systems |
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MP8763D Fiches technique(HTML) 17 Page - Monolithic Power Systems |
17 / 25 page MP8763D ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER MP8763D Rev. 1.1 www.MonolithicPower.com 17 1/15/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. voltage source that measures less than 5.5V through a pull-up resistor (typically 100kΩ). After VCC is ready, the MOSFET turns on so that the PG pin is pulled to GND before the SS is ready. After the FB voltage reaches 91% of the REF voltage, the PG pin is pulled high after a 2.5ms delay. When the FB voltage drops to 85% of the REF voltage or exceeds 120% of the nominal REF voltage, the PG pin is pulled low. If the input supply fails to power the MP8763D, the PG pin is also pulled low even though this pin is tied to an external DC source through a pull-up resistor (typically 100kΩ). Over-Current Protection (OCP) The MP8763D features TWO current limit levels for over-current conditions: low-side valley current limit and low-side negative current limit. Low-Side Valley Current Limit : The device monitors the inductor current during the LS-FET ON state. When ILIM=1 and at the end of the OFF time, the LS-FET sourcing current is compared to the internal positive-valley–current limit. If the valley current limit is less than the LS- FET sourcing current, the HS-FET remains OFF and the LS-FET remains ON for the next ON time. When the LS-FET sourcing current drops below the valley current limit, the HS-FET turns on again. These parts enter OCP mode if the LS-FET sourcing valley current exceeds the valley current limit for about 40us. During OCP, the device tries to recover from the over-current fault with hiccup mode: the chip disables the output power stage, discharges the soft-start capacitor and then automatically retries soft-start. If the over-current condition still holds after soft-start ends, the device repeats this operation cycle until the over- current conditions disappear and then output rises back to regulation level. OCP offers non- latch protection. Low-Side Negative Current Limit: If the sensed LS-FET negative current exceeds the negative current limit, the LS-FET turns off immediately and stays OFF for the remainder of the OFF period. In this situation, both MOSFETs are OFF until the end of a fixed interval. The HS-FET body diode conducts the inductor current for the fixed time. Over -Voltage Protection (OVP) The MP8763D monitors the output voltage using the FB pin connected to the tap of a resistor divider to detect over-voltage. MP8763D provides non-latch OVP mode. If the FB voltage exceeds the nominal REF voltage but remains lower than 120% of the REF voltage (0.611V), both MOSFETs are off. If the FB voltage exceeds 120% of the REF voltage but remains below 130%, the LS-FET turns on while the HS-FET remains off. The LS- FET remains on until the FB voltage drops below 110% of the REF voltage or the low-side negative current limit is hit. If the FB voltage exceeds 130% of the REF voltage, these parts enter a non-latch off mode. Once the FB voltage comes back to the reasonable value, they will exit this OVP mode and operate normally again. UVLO protection The MP8763D has under-voltage lock-out protection (UVLO). When the VCC voltage exceeds the UVLO rising threshold voltage, the MP8763D powers up. It shuts off when the VCC voltage falls below the UVLO falling threshold voltage. This is non-latch protection. The MP8763D is disabled when the VCC voltage falls below typically 3.4V. If an application requires a higher UVLO threshold, use the two external resistors connected to the EN pin as shown in Figure 9 to adjust the startup input voltage. For best results, use the enable resistors to set the input voltage falling threshold (VSTOP) above 3.6 V. Set the rising threshold (VSTART) to provide enough hysteresis to account for any input supply variations. |
Numéro de pièce similaire - MP8763D |
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Description similaire - MP8763D |
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