ACT510x

Rev 1.0, 04-Apr-2018

12

3. Device Power Up

3.1.Power-On-Reset (POR)

When VIN or VOUT is above 3.9V, the I2C bus is ready for communication and the VREF LDO is enabled. All registers are

reset to the default value as listed in the register map.

3.2.HIZ Mode

The device goes into HIZ mode when EN is pin HI, or HIZ Register 0x00 Bit 7 is set HI. At HIZ mode, the internal bias

circuits are enabled, all registers are accessible and ADC functions can be enabled. If the VREG_EN Register 0x01 Bit 2

is HI, then the VREG LDO will be enabled.

3.3.VREG LDO

The VREG LDO is powered from VIN or VOUT with a smart active diode selector circuit.

To reduce power dissipation, the VREG LDO will be powered from the lower of the VIN or VOUT. However, if the lower

supply cannot provide the headroom needed to regulate VREG output, it will select the higher supply.

This smart diode selector can be overridden and manual control can be selected using the VREG_OVERRIDE and

VREG_SELECT Registers 0x0B, bits 1:0.

The VREG is enabled when all the conditions are valid:



VIN or VOUT above UVLO (3.9V)



VREG_DIS Register is bit is set LO (Register 0x01 Bit 2)



This register bit can be programmed from the factor to be HI or LO depending on the application requirements

The voltage of VREG LDO can be set by Register 0x11 [7:3] between 2V to 5.1V. The maximum output current is 100mA.

If VREG LDO is overloaded or not within spec, converter will be shut down, and VREG_OC_UVLO fault bit Register 0x05

Bit 4 is set.

Additionally, if the VREG_LDO is held in current limit for more than 50usec, it will shut down for 100msec to prevent damage.

It will then re-try to start after 100msec. It will continue this cycle until the current limit condition is removed. Additionally,

there is a UVLO detection for the VREG output set at 88%.

If the VREG output is in current limit, or below the UVLO threshold, the converter will be in a Fault state or Reset state and

not operate. This can be overwritten with DIS_ VREG_FLT Register 0x10 Bit 1.

To reduce inrush current, a 250usec soft-start is included. For stability, a 1uF ceramic capacitor is required on the output.

4. Host Mode and Default Mode

The ACT510x is a host controlled device, but it can operate in default mode without host management. In default mode,

ACT510x can be used an autonomous converter with no host or with host in sleep. In this mode, the WATCHDOG[1:0]

Register 0x01 Bits 1:0 must be set LO to disable the watchdog timer. Additional register bits may need to be set to allow

this mode.

5. Converter Operation

The ACT510x can be enabled if the conditions are valid (see operating states for further details):

1. EN Pin is Low or EN_OVERRIDE bit is HI

2. HIZ Register bit is low

3. EN Register bit is HI

The output voltage can be set by the internal resistor divider or the feedback resistor divider on the FB pin using the

VOUT_I2C Register 0X13 [3]. When the internal resistor divider network is used, the output voltage can be changed by