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MP2159A Fiches technique(PDF) 13 Page - Monolithic Power Systems

No de pièce MP2159A
Description  1 A, 6 V, 1.5 MHz, Low IQ, COT Synchronous Step-Down Converter in 8-pin TSOT23
Download  15 Pages
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Fabricant  MPS [Monolithic Power Systems]
Site Internet  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP2159A Fiches technique(HTML) 13 Page - Monolithic Power Systems

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MP2159A – 1 A, 6 V, 1.5 MHz SYNCHRONOUS STEP-DOWN CONVERTER
MP2159A Rev. 1.02
www.MonolithicPower.com
13
6/30/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
Selecting the Output Capacitor
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic
capacitors
are
recommended.
Low
ESR
capacitors are preferred to keep the output
voltage ripple low. The output voltage ripple can
be estimated using Equation (8):
OUT
OUT
OUT
ESR
S1
IN
S
VV
1
V1
R
fL
V
8 f
C2



 


 
 
(8)
Where L1 is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
When using ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is
caused
mainly
by
the
capacitance.
For
simplification, the output voltage ripple can be
estimated using Equation (9):
OUT
OUT
OUT
2
IN
S1
VV
ΔV1
V
8f
L
C2

 

 

(9)
When using tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated with
Equation (10):
OUT
OUT
OUT
ESR
IN
S1
VV
ΔV1
R
fL
V

 


(10)
The characteristics of the output capacitor
affect the stability of the regulation system.
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For the high-frequency switching
converter, a poor layout design can result in
poor line or load regulation and stability issues.
For best results, refer to Figure 3 and follow the
guidelines below:
1. Place the high current paths (GND, VIN,
and SW) very close to the device with
short, direct, and wide traces.
2. Place the input capacitor as close as
possible to VIN and GND.
3. Place the external feedback resistors
next to FB.
4. Keep the switching node (SW) short and
away from the feedback network.
8
7
6
5
L1
R4
R3
1
2
3
4
OUT
VIN
GND
SW
C1
C1A
Figure 3—Recommended PCB layout
Design Example
Table 2 shows a design example following the
application
guidelines
for
the
given
specifications:
Table 2—Design example
VIN
5 V
VOUT
1.2 V
fSW
1500 kHz
The detailed application schematic is shown in
Figure 4. The typical performance and circuit
waveforms have been shown in the “Typical
Performance Characteristics” section. For more
device applications, please refer to the related
evaluation board datasheets.


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