OV6630 datasheet(12/29 Pages) ETC

No de pièce	OV6630

Description	SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

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Fabricant	ETC [List of Unclassifed Manufacturers]

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

March 4, 2000

Version 1.0

12

Executing a software power down through the I

2C interface suspends

internal circuit activity, but does not halt the device clock. The current

requirements drop to less than 1mA in this mode.

1.2.11

Configure OV6630/OV6130

Two methods are provided to configure OV6630/OV6130 for specific

application requirements.

At power up, OV6630/OV6130 reads the status of certain pins to

determine what, if any, power up pin programming default settings

are requested. Once the reading of the external pins status is

completed, the device configures its internal registers according to the

specified pins. Not all device functions are available for configuration

through external pins. Power up pin programming occurs in 1024

system clock cycles.

A

more

flexible

and

comprehensive

method

to

configure

OV6630/OV6130 is to use its on-chip I

2C register programming

capability. The I

2C interface provides access to all of the device’s

programmable internal registers. See I2C Bus Protocol Format for

further details about using the I

2C interface on the OV6630/OV6130

camera device.

CLK

HSYNC

VSYNC

1 Line=472 T

CLK

1 Frame=625 x 472 T

CLK

T

CLK

T

HS

T

VS

Notes:

T

HS > 6 TCLK (2), THS < TVS < 472 TCLK

HSYNC period is (472 T

CLK)

VSYNC period is (625 x 472 T

CLK)

OV6630/OV6130 will be stable after 1 field (2nd VSYNC)

Figure 6. Slave Mode External Sync Timing

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OV6630 Fiches technique(PDF) 12 Page - List of Unclassifed Manufacturers

OV6630 Fiches technique(HTML) 12 Page - List of Unclassifed Manufacturers

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