FM21L16

Document Number: 001-86191 Rev. *D

Page 3 of 22

Pinout

Figure 1. 44-pin TSOP II pinout

Pin Definitions

Pin Name

I/O Type

Description

Input

Address inputs

: The 17 address lines select one of 128K words in the F-RAM array. The lowest two

WE

Input

Write Enable

: A write cycle begins when WE is asserted. The rising edge causes the FM21L16 to write

the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for

page mode write cycles.

CE

Input

Chip Enable

: The device is selected and a new memory access begins on the falling edge of CE. The

page mode operation.

OE

Input

Output Enable

: When OE is LOW, the FM21L16 drives the data bus when the valid read data is

available. Deasserting OE HIGH tristates the DQ pins.

UB

Input

Upper Byte Select

If the user does not perform byte writes and the device is not configured as a 256 K × 8, the UB and LB

pins may be tied to ground.

LB

Input

Lower Byte Select

If the user does not perform byte writes and the device is not configured as a 256 K × 8, the UB and LB

pins may be tied to ground.

ZZ

Input

Sleep

: When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current

Ground

Ground for the device. Must be connected to the ground of the system.

Power supply Power supply input to the device.

NC

No connect No connect. This pin is not connected to the die.

LB

CE

NC

UB

OE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

44-pin TSOP II

Top View

(not to scale)

WE

(× 16)

ZZ