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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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CAT28C64BPA-15 Fiches technique(PDF) 7 Page - Catalyst Semiconductor |
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CAT28C64BPA-15 Fiches technique(HTML) 7 Page - Catalyst Semiconductor |
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7 / 12 page  CAT28C64B 7 Doc. No. 25006-0A 2/98 P-1 ADDRESS CE OE WE tRC DATA OUT DATA VALID DATA VALID tCE tOE tOH tAA tOHZ tHZ VIH HIGH-Z tLZ tOLZ Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. DEVICE OPERATION Read Data stored in the CAT28C64B is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architec- ture can be used to eliminate bus contention in a system environment. Figure 3. Read Cycle 28C64B F06 Figure 4. Byte Write Cycle [WE Controlled] ADDRESS CE OE WE DATA OUT tAS DATA IN DATA VALID HIGH-Z tCS tAH tCH tWC tOEH tBLC tDH tDS tOES tWP 5096 FHD F06 |
Numéro de pièce similaire - CAT28C64BPA-15 |
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Description similaire - CAT28C64BPA-15 |
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