Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

CY7C1460KV33 Fiches technique(PDF) 7 Page - Cypress Semiconductor

No de pièce CY7C1460KV33
Description  36-Mbit (1M36/2M18) Pipelined SRAM with NoBL??Architecture (With ECC)
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1460KV33 Fiches technique(HTML) 7 Page - Cypress Semiconductor

Back Button CY7C1460KV33 Datasheet HTML 3Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 4Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 5Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 6Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 7Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 8Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 9Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 10Page - Cypress Semiconductor CY7C1460KV33 Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 31 page
background image
Document Number: 001-66680 Rev. *L
Page 7 of 31
CY7C1460KV33
CY7C1460KVE33
CY7C1462KVE33
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-synchronous Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK.
BWa, BWb,
BWc, BWd
Input-synchronous Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and
DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE
Input-synchronous Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-synchronous Advance/load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW to load a new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
Input-synchronous Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device.
CE2
Input-synchronous Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE3
Input-synchronous Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
OE
Input-asynchronous Output enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
CEN
Input-synchronous Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa,DQb,DQc,
DQd
I/O-synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the
data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQPa,DQPb,
DQPc,DQPd
I/O-synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled
by BWc, and DQPd is controlled by BWd.
MODE
Input strap pin
Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE defaults HIGH, to an interleaved burst order.
TDO
JTAG serial output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI
JTAG serial input
synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
TMS
Test mode select
synchronous
This pin controls the test access port state machine. Sampled on the rising edge of TCK.
TCK
JTAG-clock
Clock input to the JTAG circuitry.


Numéro de pièce similaire - CY7C1460KV33

FabricantNo de pièceFiches techniqueDescription
logo
Cypress Semiconductor
CY7C1460KV25 CYPRESS-CY7C1460KV25 Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-167AXC CYPRESS-CY7C1460KV25-167AXC Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-167BZC CYPRESS-CY7C1460KV25-167BZC Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-167BZXI CYPRESS-CY7C1460KV25-167BZXI Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460KV25-200BZI CYPRESS-CY7C1460KV25-200BZI Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
More results

Description similaire - CY7C1460KV33

FabricantNo de pièceFiches techniqueDescription
logo
Cypress Semiconductor
CY7C1460KV25 CYPRESS-CY7C1460KV25 Datasheet
830Kb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1460SV25 CYPRESS-CY7C1460SV25 Datasheet
429Kb / 31P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1370KV33 CYPRESS-CY7C1370KV33 Datasheet
999Kb / 32P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
CY7C1440KV33 CYPRESS-CY7C1440KV33 Datasheet
3Mb / 33P
   36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)
CY7C1461KV33 CYPRESS-CY7C1461KV33 Datasheet
2Mb / 23P
   36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM with NoBL??Architecture
CY7C1370KV25 CYPRESS-CY7C1370KV25 Datasheet
2Mb / 30P
   18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1370B CYPRESS-CY7C1370B Datasheet
759Kb / 27P
   512K 횞 36/1M 횞 18 Pipelined SRAM with NoBL Architecture
CY7C1371KV33 CYPRESS-CY7C1371KV33 Datasheet
682Kb / 24P
   18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM with NoBL??Architecture (With ECC)
CY7C1441KV33 CYPRESS-CY7C1441KV33 Datasheet
1Mb / 32P
   36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM (With ECC)
CY7C1460BV25 CYPRESS-CY7C1460BV25 Datasheet
721Kb / 30P
   36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com