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LANSDALE Semiconductor, Inc.

ML145050, ML145051

AC ELECTRICAL CHARACTERISTICS

(Full Temperature and Voltage Ranges per Operation Ranges Table)

Figure

Symbol

Parameter

Guaranteed

Limit

Unit

1

f

Clock Frequency, SCLK

(10-bit xfer) Min

(11- to 16-bit xfer) Min

Note: Refer to twH, twL below

(10- to 16-bit xfer) Max)

0

Note 1

2.1

MHz

1

f

Clock Frequency, ADCLK

Minimum

Note: Refer to twH, twL below

Maximum

500

2.1

kHz

MHz

1

twH

Minimum Clock High Time

ADCLK

SCLK

190

190

ns

1

twL

Minimum Clock Low Time

ADCLK

SCLK

190

190

ns

1, 7

tPLH, tPHL Maximum Propagation Delay, SCLK to Dout

125

ns

1, 7

th

Minimum Hold Time, SCLK to Dout

10

ns

2, 7

tPLZ, tPHZ Maximum Propagation Delay, CS to Dout High-Z

150

ns

2, 7

tPZL, tPZH Maximum Propagation Delay, CS to Dout Driven

ML145050

ML145051

2 ADCLK cycles + 300

2.3

ns

µs

3

tsu

Minimum Setup Time, Din to SCLK

100

ns

3

th

Minimum Hold Time, SCLK to Din

0

ns

4, 7, 8

td

Maximum Delay Time, EOC to Dout (MSB)

ML145051

100

ns

5

tsu

Minimum Setup Time, CS to SCLK

ML145050

ML145051

2 ADCLK cycles + 425

2.425

ns

µs

–

tCSd

Minimum Time Required Between 10th SCLK Falling

ML145050

Edge ( 0.8 V) and CS to Allow a Conversion

ML145051

44

Note 2

ADCLK

cycles

–

tCAs

Maximum Delay Between 10th SCLK Falling Edge

ML145050

( 2 V) and CS to Abort a Conversion

ML145051

36

9

ADCLK

cycles

µs

5

th

Minimum Hold Time, Last SCLK to CS

0

ns

6, 8

tPHL

Maximum Propagation Delay, 10th SCLK to EOC

ML145051

2.35

µs

1

tr, tf

Maximum Input Rise and Fall Times

SCLK

ADCLK

Din, CS

1

250

10

ms

ns

µs

1, 4, 6 – 8

tTLH, tTHL Maximum Output Transition Time, Any Output

300

ns

–

Cin

Maximum Input Capacitance

AN0 – AN10

ADCLK, SCLK, CS, Din

55

15

pF

–

Cout

Maximum Three-State Output Capacitance

Dout

15

pF

NOTES:

1. After the 10th SCLK falling edge (

≤ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 38 ADCLKs (ML145050) or 18.5 µs

(ML145051).

2. On the ML145051, a CS edge may be received immediately after an active transition on the EOC pin.

Issue B