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Issue A

LANSDALE Semiconductor, Inc.

ML12054A

Characteristic

Symbol

Min

Typ

Max

Unit

Toggle Frequency (Sine Wave Input)

ft

0.1

2.5

2.0

GHz

Supply Current (Pin 2)

ICC

–

2.0

2.6

mA

Modulus Control Input High (MC)

VIH1

2.0

–

VCC + 0.5 V

V

Modulus Control Input Low (MC)

VIL1

Gnd

–

0.8

V

Divide Ratio Control Input High (SW)

VIH2

VCC – 0.5 V

VCC

VCC + 0.5 V

VDC

Divide Ratio Control Input Low (SW)

VIL2

Open

Open

Open

–

Output Voltage Swing (Note 2) (CL = 8.0 pF, RL = 1.65 kΩ)

Vout

0.8

1.1

–

Vpp

Modulus Setup Time MC to Out @ 2000 MHz

tset

–

8.0

10

ns

Input Voltage Sensitivity 250–2000 MHz

100–250 MHz

Vin

100

400

–

–

1000

1000

mVpp

Output Current (Note 1)

VCC = 2.7 V, CL = 8.0 pF, RL = 1.65 kΩ

VCC = 5.0 V, CL = 8.0 pF, RL = 3.6 kΩ

IO

–

–

1.0

1.0

4.0

4.0

mA

NOTES: 1. Divide ratio of ÷64/65 @ 2.0 GHz

2. Valid over voltage range 2.7 to 5.5 V; RL = 1.65 kΩ @ VCC = 2.7 V; RL = 3.6 kΩ @ VCC = 5.0 V

A

H

G

F

E

D

In

MC

In

SW

Out

Q

S

Q

C

QB

D

Q

C

QB

D

QB

C

Q

D

C

QB

D

QB

C

Q

D

QB

C

Q

D

B

QB

C

Q

D

C

QB

C

Q

D

M

Modulus setup time MC to out is the MC

setup or MC release plus the prop delay.

Prop. Delay

In

Out

MC

MC Setup

MC Release

Figure 1. Logic Diagram (ML12054A)

Figure 2. Modulus Setup Time

Figure 3. AC Test Circuit

EXTERNAL COMPONENTS

C1 = C2 = 1000 pF

C3 = 0.1 µF

CL = 8.0 pF (Including Scope

and jig capacitance)

RL = 1.65 kΩ @ VCC = 2.7 V

RL = 3.6 kΩ @ VCC = 5.0 V

CL

MC Input

C2

C1

C3

VCC = 2.7 to 5.5 V

50 Ω

Sine Wave Generator

SW

VCC

OUT

GND

MC

IN

IN

RL