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AD7228 Fiches technique(PDF) 5 Page - Analog Devices |
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AD7228 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 16 page AD7228 Data Sheet Rev. D | Page 4 of 15 SINGLE SUPPLY VDD = 15 V ± 10%, VSS = GND, GND = 0 V, VREF = 10 V, RL = 2 kΩ, CL = 100 pF, unless otherwise noted. All specifications TMIN to TMAX, −40°C to +85°C, unless otherwise noted. Table 2. Parameter K and B Versions L and C Versions Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 8 8 Bits Total Unadjusted Error1 ±2 ±1 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic Minimum Load Resistance 2 2 kΩ min VOUT = 10 V REFERENCE INPUT Input Resistance 2 2 kΩ min Input Capacitance2 500 500 pF max Occurs when each DAC is loaded with all 1s DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Leakage Current ±1 ±1 µA max VIN = 0 V or VDD Input Capacitance2 8 8 pF max Input Coding Binary Binary DYNAMIC PERFORMANCE2 Voltage Output Slew Rate 2 2 V/µs min Voltage Output Settling Time Positive Full-Scale Change 5 5 µs max Settling time to ±1/2 LSB Negative Full-Scale Change 7 7 µs max Settling time to ±1/2 LSB Digital Feedthrough 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 0 V, WR = VDD Digital Crosstalk3 50 50 nV-sec typ Code transition all 0s to all 1s, VREF = 10 V, WR = 0 V POWER SUPPLIES VDD Range 13.5/16.5 13.5/16.5 V min/V max For specified performance IDD Outputs unloaded; VIN = VINL or VINH at 25°C 16 16 mA max TMIN to TMAX 20 20 mA max 1 Total unadjusted error includes zero code error, relative accuracy and full-scale error. 2 Sample tested at TA = 25°C to ensure compliance. 3 The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. |
Numéro de pièce similaire - AD7228 |
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Description similaire - AD7228 |
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