CS5323GDWR20 datasheet(9/16 Pages) ONSEMI

No de pièce	CS5323GDWR20

Description	Three-Phase Buck Controller with 5-Bit DAC

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Fabricant	ONSEMI [ON Semiconductor]

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CS5323

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9

APPLICATIONS INFORMATION

FIXED FREQUENCY MULTI–PHASE CONTROL

In a multi–phase converter, multiple converters are

connected in parallel and are switched on at different times.

This reduces output current from the individual converters

and increases the apparent ripple frequency. Because several

converters are connected in parallel, output current can ramp

up or down faster than a single converter (with the same

value output inductor) and heat is spread among multiple

components.

The CS5323 uses a three–phase, fixed frequency,

enhanced V2 architecture. Each phase is delayed 120

° from

the previous phase. Normally the GATE transitions high at

the beginning of each oscillator cycle. Inductor current

ramps up until the combination of the current sense signal

and the output ripple trip the PWM comparator and bring the

GATE low. Once the GATE goes low, it will remain low until

the beginning of the next oscillator cycle. While the GATE

is high, the enhanced V2 loop will respond to line and load

transients. Once the GATE is low, the loop will not respond

again until the beginning of the next cycle. Therefore,

constant frequency, enhanced V2 will typically respond

within the off–time of the converter.

The enhanced V2 architecture measures and adjusts

current in each phase. An additional input (CX) for inductor

current information has been added to the V2 loop for each

phase as shown in Figure 5.

Figure 5. Enhanced V2 Feedback and Current

Sense Scheme

CSREF

VOUT

SWNODE

CSX

VFB

L

RL

RS

COMP

DACOUT

+

E.A.

+

OFFSET

CSA

PWM

COMP

The inductor current is measured across RS, amplified by

CSA and summed with the OFFSET and Output Voltage at

the non–inverting input of the PWM comparator. The

inductor current provides the PWM ramp and as inductor

current increases the voltage on the positive pin of the pwm

comparator rises and terminates the pwm cycle. If the

inductor starts the cycle with a higher current the PWM

cycle will terminate earlier providing negative feedback.

The CS5323 provides a CX input for each phase, but the

CSREF, VFB and COMP inputs are common to all phases.

Current sharing is accomplished by referencing all phases to

the same VFB and COMP pins, so that a phase with a larger

current signal will turn off earlier than phases with a smaller

current signal.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. If the COMP pin is held

steady and the inductor current changes there must also be

a change in the output voltage. Or, in a closed loop

configuration when the output current changes, the COMP

pin must move to keep the same output voltage. The required

change in the output voltage or COMP pin depends on the

scaling of the current feedback signal and is calculated as

DV + RS

CSA Gain

DI

The single–phase power stage output impedance is;

Single Stage Impedance

+ DV DI + RS

CSA Gain.

The multi–phase power stage output impedance is the

single–phase output impedance divided by the number of

phases. The output impedance of the power stage determines

how the converter will respond during the first few

µs of a

transient before the feedback loop has repositioned the

COMP pin.

The peak output current of each phase can also be

calculated from;

Ipkout (per phase) +

VCOMP * VFB * VOFFSET

RS

CSA Gain

Figure 6 shows the step response of a single phase with the

COMP pin at a fixed level. Before T1 the converter is in

normal steady state operation. The inductor current provides

the pwm ramp through the Current Share Amplifier. The

pwm cycle ends when the sum of the current signal, voltage

signal and OFFSET exceed the level of the COMP pin. At

T1 the output current increases and the output voltage sags.

The next pwm cycle begins and the cycle continues longer

than previously while the current signal increases enough to

make up for the lower voltage at the VFB pin and the cycle

ends at T2. After T2 the output voltage remains lower than

at light load and the current signal level is raised so that the

sum of the current and voltage signal is the same as with the

original load. In a closed loop system the COMP pin would

move higher to restore the output voltage to the original

level.

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