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TPS2140 Fiches technique(PDF) 4 Page - Texas Instruments

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No de pièce TPS2140
Description  ADJUSTABLE LDO AND SWITCH WITH DUAL CURRENT LIMIT FOR USB HIGH-POWER PERIPHERAL POWER MANAGEMENT
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS2140 Fiches technique(HTML) 4 Page - Texas Instruments

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TPS2140, TPS2141
TPS2150, TPS2151
SLVS399 – JANUARY 2002
4
www.ti.com
detailed description
GND
Ground
SW_IN
SW_IN is the input to an integrated N-channel MOSFET, which has a maximum on-state resistance of 65 m
Ω.
Configured as a high-side switch, the power switch prevents current, flow from OUT to IN and IN to OUT when
disabled. The power switch is rated at 500 mA, continuous current and has a dual current limit feature.
dual current limit
The current limiter for the switch limits the initial current drawn from SW_IN to 100 mA maximum. The user can
estimate the amount of time it takes to charge a capacitor (CL) connected to SW_OUT by using the following
relationship:
CL
× VI(SW_IN) / 0.1 < tCHG < CL × VI(SW_IN) / 0.05
Capacitance in farads. If VI(SW_IN) = 5 V, then
50
× CL< tCHG <100 × CL
When the voltage at output SW_OUT rises above 93% of the voltage at SW_IN, the current limit is increased
to 1800 mA maximum. The SW_PG can be used to turn on loads which may draw more than 50 mA.
In the event of an overload on SW_OUT, the protection circuit limits the current delivered to 1800 mA maximum.
As the output voltage drops and it crosses 80% of the SW_IN voltage, the current limiter reverts back to the
low-current limit mode of 100 mA maximum.
SW_IN also serves as one of the two inputs to an internal voltage selector that provides operating voltage to
the whole device. The other input to the selector is LDO_IN.
SW_OUT
SW_OUT is the output of the internal power-distribution switch.
SW_EN or SW_EN
The logic input disables or enables the power switch. This signal is active low (SW_EN) for TPS2140/41 and
active high (SW_EN) for TPS2150/51. SW_EN has an internal pullup and SW_EN has an internal pulldown.
SW_PG
SW_PG signals the presence of an undervoltage condition on SW_OUT. The pin is driven by a CMOS output
buffer and is pulled low during an undervoltage condition. To minimize erroneous SW_PG responses from
transients on the voltage rail, the voltage sense circuit incorporates a rising and falling edge deglitch filter. When
SW_OUT voltage is lower than 88% of 3.3 V for TPS2140/50, or 5 V for TPS2141/51, SW_PG goes low to
indicate an undervoltage condition on SW_OUT.
SW_PLDN
SW_PLDN is an open drain output incorporated to provide a discharge path. When the power switch is on, this
pin is open; otherwise it is pulled down to ground. When this pin is connected to SW_OUT, the output voltage
fall time is reduced but the rise time remains unaffected.
LDO_IN
The LDO_IN serves as the input to the internal LDO. The adjustable LDO has a dropout voltage of 0.5 V
maximum and is rated for 250 mA of continuous current. LDO_IN is also used as one of the two inputs for VCC
selection.


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