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SLG46531 Fiches technique(PDF) 38 Page - Dialog Semiconductor |
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SLG46531 Fiches technique(HTML) 38 Page - Dialog Semiconductor |
38 / 170 page SLG46531_DS_109 Page 37 of 169 SLG46531 7.6 Matrix OE IO Structure 7.6.1 Matrix OE IO Structure (for Pins 3, 5, 7, 13, 14, 16, 18, 19) Figure 3. Matrix OE IO Structure Diagram PAD S0 S1 pull_up_en 10 k 90 k 900 k Res_sel[1:0] 00: floating 01: 10 k 10: 100 k 11: 1 M Input Mode [1:0] 00: Digital In without Schmitt Trigger, wosmt_en=1 01: Digital In with Schmitt Trigger, smt_en=1 10: Low Voltage Digital In mode, lv_en = 1 11: Analog IO mode Output Mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x NMOS open drain mode, od1x_en=1 11: 2x NMOS open drain mode, od2x_en=1, od1x_en=1 Note: Digital Out and OE are Matrix output, Digital In is Matrix input (For PINs 7, 13, 14, 18 and 19 only) Digital Out Digital Out OE od2x_en OE od1x_en Digital Out OE pp2x_en Digital Out OE pp1x_en Digital In Low Voltage Input Non-Schmitt Trigger Input Analog IO OE lv_en Schmitt Trigger Input OE smt_en OE wosmt_en |
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