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SLG46200 Fiches technique(PDF) 53 Page - Dialog Semiconductor |
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SLG46200 Fiches technique(HTML) 53 Page - Dialog Semiconductor |
53 / 69 page 000-0046200-124 Page 48 of 64 SLG46200 19.0 Digital Storage Elements (DFFs/LATCHes) There are three DFF/LATCHes logic cells within the SLG46200 available for design. The source and destination of the inputs and outputs for the three DFF/LATCHes are configured from the connection matrix. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CK = 0, then Q = D if CK = 1, then Q will not change 19.1 DFF/LATCH Functional Diagram 19.2 DFF/LATCH Selection Each of the three DFF/LATCH logic cells has a selection bit that is used to define if the logic cell will be used as a D Flip-Flop or a Latch within the design. Those control bits are shown in the table below. 19.3 DFF/LATCH Register Settings Figure 33. DFF/LATCH Functional Diagram Table 29. DFF/LATCH Register Settings Signal Function Register Bit Address Register Definition DFF/LATCH0 Selection <315> 0: DFF 1: LATCH DFF/LATCH1 Selection <316> 0: DFF 1: LATCH DFF/LATCH2 Selection <317> 0: DFF 1: LATCH DFF/ LATCH0 CK D To Connection Matrix input <8> Q reg <315> From Connection Matrix output <22> From Connection Matrix output <23> DFF/ LATCH1 CK D To Connection Matrix input <9> Q reg <316> From Connection Matrix output <24> From Connection Matrix output <25> DFF/ LATCH2 CK D To Connection Matrix input <10> Q reg <317> From Connection Matrix output <26> From Connection Matrix output <27> |
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