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PV88090 Fiches technique(PDF) 19 Page - Dialog Semiconductor

No de pièce PV88090
Description  High Efficiency 3-Channel Buck Converter with dual LDO
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PV88090
High Efficiency 3-Channel Buck Converter with dual LDO
Datasheet
Revision 1.0
10-Dec-2017
CFR0011-120-00
19 of 42
© 2017 Dialog Semiconductor
6.1.7
I2C Interface
The I2C interface provides access to control and status registers. The interface supports operations
compatible to standard, fast, fast-plus, and high-speed mode of the I2C bus specification.
Communication on the I2C bus is always between two devices, one acting as the master and the
other as the slave. PV88090 will only operate as a slave. The I2C interface has direct access to two
pages of the PV88090 register map (up to 256 addresses).
SCL carries the I2C clock and SDA carries the bi-directional data. The I2C interface is open drain
supporting multiple devices on a single line. The bus lines have to be pulled high by external pull-up
resistors (2 kΩ to 20 kΩ). The attached devices only drive the bus lines low by connecting them to
ground. As a result, two devices cannot conflict if they drive the bus simultaneously. In standard/fast
mode the highest frequency of the bus is 400 kHz. The exact frequency can be determined by the
application and it does not have any relation to the PV88090 internal clock signals. PV88090 will
synchronize with the host clock speed within the described limitations and will not initiate any clock
arbitration or slow down.
If SDA is stuck the bus clears after receiving 9 clock pulses. Operation in high speed mode at 3.4
MHz requires a minimum 1.8 V interface supply voltage and a mode change in order to enable spike
suppression and slope control characteristics compatible to the I2C specification.
6.1.8
I2CProtocol
All data is transmitted across the I2C bus in 8 bit groups. To send a bit the SDA line is driven to the
intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and then
low. This pulse on SCL clocks the SDA bit into the receiver
’s shift register.
A two-byte serial protocol is used containing one byte for address and one byte data. Data and
address transfer is transmitted MSB first for both read and write operations. All transmission begins
with the START condition from the master during which the bus is in IDLE state (the bus is free). It is
initiated by a high-to-low transition on the SDA line while the SCL is in the high state. A STOP
condition is indicated by a low-to-high transition on the SDA line while the SCL is in the high state.
The START and STOP conditions are illustrated in Figure 4.
SCL
SDA
Figure 4: Timing of the START and STOP conditions
The I2C bus is monitored by PV88090 for a valid slave address whenever the interface is enabled. It
responds immediately when it receives its own slave address. The acknowledge is achieved by
pulling the SDA line low during the following clock cycle: white blocks marked with A in the following
figures.
The protocol for a register write from master to slave consists of a START condition, a slave address,
a read/write-bit, 8-bit address, 8-bit data, and a STOP condition. PV88090 responds to all bytes with
an ACK.
SLAVEadr
W
REGadr
A
DATA
A
P
S = START condition
A = Acknowledge (low)
P = STOP condition
W = Write (low)
Master to Slave
Slave to Master
7-bits
1-bit
8-bits
8-bits
A
S
Figure 5: Byte Write Operation


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