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ST16C554D Fiches technique(PDF) 11 Page - Exar Corporation |
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ST16C554D Fiches technique(HTML) 11 Page - Exar Corporation |
11 / 40 page ST16C554/554D/68C554 11 Rev. 3.10 GENERAL DESCRIPTION The 554D provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integ- rity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The ST16C554D represents such an integration with greatly enhanced features. The 554D is fabri- cated with an advanced CMOS process to achieve low drain power and high speed requirements. The 554D is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 1 bytes provided in the 16/68C454. The 554D is de- signed to work with high speed modems and shared network environments, that require fast data process- ing time. Increased performance is realized in the 554D by the larger transmit and receive FIFOs. This allows the external processor to handle more network- ing tasks within a given time. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. The 554D combines the package interface modes of the 16C554D and 68C554 series on a single inte- grated chip. The 16 mode interface is designed to operate with the Intel type of microprocessor bus while the 68 mode is intended to operate with Motorola, and other popular microprocessors. Following a reset, the 554D is down-ward compatible with the ST16C454/ ST68C454 dependent on the state of the interface mode selection pin, 16/-68. The 554D is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz, the user can select data rates up to 921.6Kbps. The rich feature set of the 554D is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, modem interface controls. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software con- trolled or continuous interrupt capability. Due of pin limitations for the 64 pin 554D this feature is offered by two different QFP packages. The ST16C554DCQ64 operates in the continuos interrupt enable mode by bonded INTSEL to VCC internally. The ST16C554CQ64 operates in conjunction with MCR bit-3 by bonding INTSEL to GND internally. FUNCTIONAL DESCRIPTIONS Interface Options Two user interface modes are selectable for the 554D package. These interface modes are designated as the 16 mode and the 68 mode. This nomenclature corresponds to the early 16C554D and 68C554 pack- age interfaces respectively. The 16 Mode Interface The 16 mode configures the package interface pins for connection as a standard 16 series (Intel) device and operates similar to the standard CPU interface avail- able on the 16C554D. In the 16 mode (pin 16/-68 logic 1) each UART is selected with individual chip select (CSx) pins as shown in Table 2 below. Table 2, SERIAL PORT CHANNEL SELECTION GUIDE, 16 MODE INTERFACE -CSA -CSB -CSC -CSD UART CHANNEL 1111 None 0111 A 1011 B 1101 C 1110 D |
Numéro de pièce similaire - ST16C554D |
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Description similaire - ST16C554D |
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