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TSB41BA3PFP Fiches technique(PDF) 8 Page - Texas Instruments |
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TSB41BA3PFP Fiches technique(HTML) 8 Page - Texas Instruments |
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8 / 63 page  TSB41BA3 IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER SLLS155A − MAY 2003 − REVISED OCTOBER 2003 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME TYPE NO. I/O DESCRIPTION LCLK_PMC CMOS 7 I Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY. On hardware reset this terminal is sampled to determine the power management control (PMC) mode. LCLK_PMC LPS BMODE Mode H L H No LLC (PMC mode) n/c† lps L Legacy LLC LCLK_PMC‡ lps H Beta LLC † internal pulldown on LCLK_PMC ‡ LCLK_PMC from LLC normally low during reset In PMC mode, since no LLC is attached the data lines (D7−D0) are available to indicate power states. In PMC mode the following signals are output: − D0—port 0 cable-power disable (see Note 1) − D1—port 1 cable-power disable (port in sleep or disabled) − D2—port 2 cable-power disable (port in sleep or disabled) − D6—All ports cable-power disable (all ports in sleep/disable) logical AND of bits 0−2 − D3−D5 and D7 are reserved for future use. Note 1: The cable-power disable is asserted when the port is either: − Hard-disabled (both the disabled and hard disabled bits are set) − Sleep-disabled (both the disabled and sleep_enable bits are set) − Disconnected − Asleep − Connected in DS mode, but nonactive (that is, suspended or disabled) Otherwise, the cable-powered disable output is deasserted (that is, cable power enabled) when the port is dc-connected or active. A bus holder is built into this terminal. LPS CMOS 80 I Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the VDD supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the LLC and PHY (see Figure 8). The LPS input is considered inactive if it is sampled low by the PHY for more than a LPS_RESET time (~2.6 µs), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 22 ns to be guaranteed to be observed as high by the PHY. When the TSB41BA3 detects that the LPS input is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than a LPS_DISABLE time (~26 µs), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC state that is communicated in the self-ID packet is considered active only if both the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB41BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). LREQ CMOS 3 I LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3. A bus holder is built into this terminal. PCLK CMOS 5 O PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is in legacy 1394a-2000 (BMODE input deasserted). PD CMOS 77 I Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD input high also activates an internal pulldown on the RESETz terminal to force a reset of the internal control logic. PINT CMOS 1 O PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal. PLLGND Supply 25, 28 − PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. |
Numéro de pièce similaire - TSB41BA3PFP |
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Description similaire - TSB41BA3PFP |
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