List of figures

VND7012AY

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DocID027407 Rev 4

List of figures

Figure 1: Block diagram ..............................................................................................................................5

Figure 2: Configuration diagram (top view).................................................................................................6

Figure 3: Current and voltage conventions.................................................................................................7

Figure 4: IOUT/ISENSE vs. IOUT.............................................................................................................17

Figure 5: Current sense precision vs. IOUT .............................................................................................17

Figure 6: Switching times and Pulse skew ...............................................................................................18

Figure 7: MultiSense timings (current sense mode) .................................................................................18

Figure 8: MultiSense timings (chip temperature and VCC sense mode) .................................................19

Figure 9: TDSKON....................................................................................................................................19

Figure 10: OFF-state output current .........................................................................................................21

Figure 11: Standby current .......................................................................................................................21

Figure 12: IGND(ON) vs. Iout ...................................................................................................................21

Figure 13: Logic Input high level voltage ..................................................................................................21

Figure 14: Logic Input low level voltage....................................................................................................21

Figure 15: High level logic input current ...................................................................................................21

Figure 16: Low level logic input current ....................................................................................................22

Figure 17: Logic Input hysteresis voltage .................................................................................................22

Figure 18: FaultRST Input clamp voltage .................................................................................................22

Figure 19: Undervoltage shutdown ...........................................................................................................22

Figure 20: On-state resistance vs. Tcase .................................................................................................22

Figure 21: On-state resistance vs. VCC ...................................................................................................22

Figure 22: Turn-on voltage slope ..............................................................................................................23

Figure 23: Turn-off voltage slope ..............................................................................................................23

Figure 24: Won vs. Tcase .........................................................................................................................23

Figure 25: Woff vs. Tcase .........................................................................................................................23

Figure 26: ILIMH vs. Tcase.......................................................................................................................23

Figure 27: OFF-state open-load voltage detection threshold ...................................................................23

Figure 28: Vsense clamp vs. Tcase..........................................................................................................24

Figure 29: Vsenseh vs. Tcase ..................................................................................................................24

Figure 30: Application diagram .................................................................................................................26

Figure 31: Simplified internal structure .....................................................................................................26

Figure 32: MultiSense and diagnostic

– block diagram ............................................................................28

Figure 33: MultiSense block diagram .......................................................................................................29

Figure 34: Analogue HSD

– open-load detection in off-state ...................................................................30

Figure 35: Open-load / short to VCC condition.........................................................................................31

Figure 36: GND voltage shift ....................................................................................................................32

Figure 37: Maximum turn off current versus inductance ..........................................................................33

Figure 38: PowerSSO-36 PCB board .......................................................................................................34

Figure 39: Rthj-amb vs PCB copper area in open box free air condition (one channel on) .....................35

Figure 40: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ..............36

Figure 41: Thermal fitting model of a double-channel HSD in PowerSSO-16..........................................36

Figure 42: PowerSSO-36 package outline ...............................................................................................38

Figure 43: PowerSSO-36 reel 13" ............................................................................................................40

Figure 44: PowerSSO-36 carrier tape ......................................................................................................41

Figure 45: PowerSSO-36 schematic drawing of leader and trailer tape ..................................................42

Figure 46: PowerSSO-36 marking information .........................................................................................42