Moteur de recherche de fiches techniques de composants électroniques |
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ICX285AQ Fiches technique(PDF) 2 Page - Sony Corporation |
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ICX285AQ Fiches technique(HTML) 2 Page - Sony Corporation |
2 / 23 page – 2 – ICX285AQ Block Diagram and Pin Configuration (Top View) Pin No. Pin No. Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal output Supply voltage Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Substrate clock Substrate bias∗1 Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock ∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. Pin Description 11 12 13 14 15 16 17 18 19 20 Note) Note) : Photo sensor Horizontal register 10 9 8 7 6 5 4 3 2 1 B G B G B G R G R G B G B G B G R B G G R B G G R G R G G R G R Symbol Description V φ1 V φ2A NC V φ2B NC NC V φ4 V φ3 GND GND Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND GND Symbol VOUT VDD φRG H φ2 H φ1 φSUB CSUB VL H φ1 H φ2 |
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Description similaire - ICX285AQ |
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