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MT9V024 Fiches technique(PDF) 24 Page - ON Semiconductor

No de pièce MT9V024
Description  1/3-Inch Wide VGA CMOS Digital Image Sensor
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MT9V024 Fiches technique(HTML) 24 Page - ON Semiconductor

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Bit 0 is used to reset the digital logic of the sensor while
preserving the existing two−wire serial interface
configuration. Furthermore, by asserting the soft reset, the
sensor aborts the current frame it is processing and starts
a new frame. Bit 1 is a shadowed reset control register bit to
explicitly reset the automatic gain and exposure control
feature.
These two bits are self−resetting bits and also return to “0”
during two−wire serial inter−face reads.
STANDBY Control
The sensor goes into standby mode by setting STANDBY
to HIGH. Once the sensor detects that STANDBY is
asserted, it completes the current frame before disabling the
digital logic, internal clocks, and analog power enable
signal. To release the sensor out from the standby mode,
reset STANDBY back to LOW. The LVDS must be powered
to ensure that the device is in standby mode. See ”Appendix
A: Power−On Reset and Standby Timing” for more
information on standby.
Monitor Mode Control
Monitor mode is controlled by:
R0xD9 Monitor Mode Enable
R0xC0 Monitor Mode Image Capture Control
The sensor goes into monitor mode when R0xD9[0] is set
to HIGH. In this mode, the sensor first captures
a programmable number of frames (R0xC0), then goes into
a sleep period for five minutes. The cycle of sleeping for five
minutes and waking up to capture a number of frames
continues until R0xD9[0] is cleared to return to normal
operation.
In some applications when monitor mode is enabled, the
purpose of capturing frames is to calibrate the gain and
exposure of the scene using automatic gain and exposure
control feature. This feature typically takes less than 10
frames to settle. In case a larger number of frames is needed,
the value of R0xC0 may be increased to capture more
frames.
During the sleep period, none of the analog circuitry and
a very small fraction of digital logic (including
a five−minute timer) is powered. The master clock
(SYSCLK) is therefore always required.
READ MODE OPTIONS
(Also see “Output Data Format” and “Output Data
Timing”.)
Column Flip
By setting bit 5 of R0x0D or R0x0E the readout order of
the columns is reversed, as shown in Figure 30.
Row Flip
By setting bit 4 of R0x0D or R0x0E the readout order of
the rows is reversed, as shown in Figure 31.
Figure 30. Readout of Six Pixels in Normal and Column Flip Output Mode
LINE_VALID
Normal readout
DOUT(9:0
)
Reverse readout
DOUT(9:0
)
P4,1
(9:0)
P4,2
(9:0)
P4,3
(9:0)
P4,4
(9:0)
P4,5
(9:0)
P4,6
(9:0)
P4,n
(9:0)
P4,n−1
(9:0)
P4,n−2
(9:0)
P4,n−3
(9:0)
P4,n−4
(9:0)
P4,n−5
(9:0)
DOUT(9:0)
DOUT(9:0)
Figure 31. Readout of Six Rows in Normal and Row Flip Output Mode
FRAME_VALID
Normal readout
DOUT(9:0
)
Reverse readout
DOUT(9:0
)
Row4
(9:0)
Row5
(9:0)
Row6
(9:0)
Row7
(9:0)
Row8
7(9:0)
Row9
(9:0)
Row484
(9:0)
Row483
(9:0)
Row482
(9:0)
Row481
(9:0)
Row480
7(9:0)
Row479
(9:0)
DOUT(9:0)
DOUT(9:0)
Pixel Binning
In addition to windowing mode in which smaller
resolutions (CIF, QCIF) are obtained by selecting a smaller
window from the sensor array, the MT9V024 also provides
the ability to down−sample the entire image captured by the
pixel array using pixel binning.


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