TPS2392

TPS2393

SLUS536C − AUGUST 2002 − REVISED AUGUST 2004

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PIN ASSIGNMENTS

DRAINSNS: Sense input for monitoring the load voltage status. The DRAINSNS pin determines the load status by

sensing the voltage level on the external pass FET drain. DRAINSNS must be pulled low with repect to −VIN (less

that the load voltage has successfully ramped up to the DC input level. DRAINSNS must be connected to the FET

drain through a small-signal blocking diode as shown in the typical application diagram. An internal pull-up maintains

a high logic level at the pin until overridden by a fully-enhanced external FET.

EN: Enable input to turn on/off power to the load. The EN pin is referenced to the −VIN potential of the circuit. When

this input is pulled high (above the nominal 1.4-V threshold), and all other input qualifications are met (supply above

device undervoltage lockout (UVLO), UVLO pin high and OVLO pin low, INSx pins pulled low) the device enables

the GATE output, and begins the ramp of current to the load. When this input is low, the linear current amplifier (LCA)

is disabled, and a large pull-down device is applied to the FET gate, disabling power to the load.

FAULT: Open-drain, active-low indication of a load fault condition. When the device EN is deasserted, or when

enabled and the load current is less than the programmed limit, this output is high impedance. If the device remains

in current regulation mode at the expiration of the fault timer, or if a fast-acting overload condition causes greater than

100-mV drop across the sense resistor, the fault is latched, the load is turned off, and the FAULT pin is pulled low

(to −VIN). The TPS2392 remains latched off for a fault, and can be reset by cycling either the EN pin or power to the

device. The TPS2393 retries the load at approximately a 1% duty cycle.

FLTTIME: Connection for user-programming of the fault timeout period. An external capacitor connected from

FLTTIME to −VIN establishes the timeout period to declare a fault condtion. This timeout protects against indefinite

current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary current spikes

or surges. The TPS2392 and TPS2393 define a fault condition as voltage at the ISENS pin at or greater than the

40-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by charging

the external capacitor to the 4-V fault threshold, then subsequently discharging it to reset the timer (TPS2392), or

discharging it at approximately 1% the charge rate to establish the duty cycle for retrying the load (TPS2393).

Whenever the internal fault latch is set (timer expired), the pass FET is rapidly turned off, and the FAULT output is

asserted.

GATE: Gate drive for external N−channel FET. When enabled, and the input supply is above the UVLO threshold,

the gate drive is enabled and the device begins charging an external capacitor connected to the IRAMP pin. This

pin voltage is used to develop the reference voltage at the non-inverting input of the internal LCA. The inverting input

is connected to the current sense node, ISENS. The LCA acts to slew the pass FET gate to force the ISENS voltage

to track the reference. The reference is internally clamped at 40 mV, so the maximum current that can be sourced

to the load is determined by the sense resistor value as IMAX

up to the input dc potential, and current demand drops off, the LCA drives the GATE output to about 14 V to fully

enhance the pass FET, completing the low-impedance supply return path for the load.

INSA: Insertion detection input pin A. The INSA and INSB inputs work together to provide an insertion detection

function for TPS2392 and TPS2393 applications. In order to turn on the FET gate drive (the GATE output), both INSA

and INSB must be pulled below the detection threshold, approximatey 1.4 V. Implementations using this feature

provide a mechanism for pulling these pins directly to −VIN potential (device ground), eliminating any threshold

ambiguity. An on-chip pull-up is provided at each INSx pin; no additional pull-up is needed to hold the pins high during

the insertion process. The insertion inputs are debounced with a nominal 2.5-ms filter.

INSB: Insertion detection input pin B. See INSA description.

IRAMP: Programming input for setting the inrush current slew rate. An external capacitor connected between this

pin and −VIN establishes the load current slew rate whenever power to the load is enabled. The device charges the

external capacitor to establish the reference input to the LCA. The closed-loop control of the LCA and pass FET acts

to maintain the current sense voltage at ISENS at the reference potential. Since the sense voltage is developed as

the drop across a resistor, the load current slew rate is set by the voltage ramp rate at the IRAMP pin. When the output

is disabled for any reason (e.g., EN deassertion, voltage or current fault, etc.), the capacitor is discharged and held

low to initialize it for the next turn-on.