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GS880Z18-66 Fiches technique(PDF) 1 Page - GSI Technology |
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GS880Z18-66 Fiches technique(HTML) 1 Page - GSI Technology |
1 / 25 page Rev: 1.10 8/2000 1/25 © 1998, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc. Preliminary GS880Z18/36T-11/100/80/66 8Mb Pipelined and Flow Through Synchronous NBT SRAMs 100 MHz–66 MHz 3.3 V VDD 2.5 V and 3.3 V VDDQ 100-Pin TQFP Commercial Temp Industrial Temp Features • 512K x 18 and 256K x 36 configurations • User configurable Pipeline and Flow Through mode • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization • Fully pin compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • Pin compatible with 2M, 4M and 16M (future) devices • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleave Burst mode • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • Clock Control, registered address, data, and control • ZZ Pin for automatic power-down • JEDEC-standard 100-lead TQFP package Functional Description The GS880Z18/36T is an 8Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS880Z18/36T may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS880Z18/36T is implemented with GSI's high performance CMOS technology and is available in a JEDEC- standard 100-pin TQFP package. -11 -100 -80 -66 Pipeline 3-1-1-1 tCycle tKQ IDD 10 ns 4.5 ns 210 mA 10 ns 4.5 ns 210 mA 12.5 ns 4.8 ns 190 mA 15 ns 5 ns 170 mA Flow Through 2-1-1-1 tKQ tCycle IDD 11 ns 15 ns 150 mA 12 ns 15 ns 150 mA 14 ns 15 ns 130 mA 18 ns 20 ns 130 mA A B C D E F R W R W R W QA DB QC DD QE QA DB QC DD QE Clock Address Read/Write Flow Through Data I/O Pipelined Data I/O Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles |
Numéro de pièce similaire - GS880Z18-66 |
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Description similaire - GS880Z18-66 |
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