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AD7923BRU Fiches technique(PDF) 6 Page - Analog Devices

No de pièce AD7923BRU
Description  4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD7923BRU Fiches technique(HTML) 6 Page - Analog Devices

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AD7923
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the part. This clock
input is also used as the clock source for the AD7923 conversion process.
2DIN
Data In. Logic Input. Data to be written to the AD7923 Control Register is provided on this input and is
clocked into the register on the falling edge of SCLK (see the Control Register section).
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7923 and framing the serial data transfer.
4, 8, 13, 16
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7923. All analog input
signals and any external reference signal should be referred to this AGND voltage. All AGND pins
should be connected together.
5, 6
AVDD
Analog Power Supply Input. The AVDD range for the AD7923 is from 2.7 V to 5.25 V. For the
0 V to 2
¥ REFIN range, AVDD should be from 4.75 V to 5.25 V.
7
REFIN
Reference Input for the AD7923. An external reference must be applied to this input. The voltage
range for the external reference is 2.5 V
±1% for specified performance.
12–9
VIN0–VIN3Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed
into the on-chip track-and-hold. The analog input channel to be converted is selected by using the
address bits ADD1 and ADD0 of the Control Register. The address bits in conjunction with the SEQ1
and SEQ0 bits allow the sequencer to be programmed. The input range for all input channels can extend
from 0 V to REFIN or from 0 V to 2
¥ REFIN as selected via the RANGE bit in the Control Register.
Any unused input channels must be connected to AGND to avoid noise pickup.
14
DOUT
Data Out. Logic Output. The conversion result from the AD7923 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7923 consists of two leading zeros, two address bits indicating which channel the conversion result
corresponds to, followed by the 12 bits of conversion data, MSB first. The output coding may be
selected as straight binary or twos complement via the CODING bit in the Control Register.
15
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface
of the AD7923 will operate.
PIN CONFIGURATION
16-Lead TSSOP
1
AD7923
SCLK
AGND
16
TOP VIEW
(Not to Scale)
2
DIN
VDRIVE
15
3
CS
DOUT
14
4
AGND
AGND
13
5
AVDD
VIN0
12
6
AVDD
VIN1
11
7
REFIN
VIN2
10
8
AGND
VIN3
9


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