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TLA2024IRUGT Fiches technique(PDF) 3 Page - Texas Instruments |
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TLA2024IRUGT Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 33 page 1 ADDR 2 NC 3 GND 4 AIN0 6 AIN2 7 AIN3 8 VDD 9 SDA Not to scale 1 ADDR 2 NC 3 GND 4 AIN0 6 NC 7 NC 8 VDD 9 SDA Not to scale 3 TLA2021, TLA2022, TLA2024 www.ti.com SBAS846 – NOVEMBER 2017 Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Device Comparison Table DEVICE RESOLUTION (Bits) MAXIMUM SAMPLE RATE (SPS) INPUT CHANNELS, DIFFERENTIAL (Single-Ended) PGA INTERFACE TLA2021 12 3300 1 (1) No I2C TLA2022 12 3300 1 (1) Yes I2C TLA2024 12 3300 2 (4) Yes I2C 6 Pin Configuration and Functions TLA2021 and TLA2022 RUG Package 10-Pin X2QFN Top View TLA2024 RUG Package 10-Pin X2QFN Top View (1) Float unused analog inputs, or tie unused analog inputs to GND. Pin Functions PIN TYPE DESCRIPTION NAME TLA2021, TLA2022 TLA2024 ADDR 1 1 Digital input I2C slave address select pin. See the I2C Address Selection section for details. AIN0 4 4 Analog input Analog input 0(1) AIN1 5 5 Analog input Analog input 1(1) AIN2 — 6 Analog input Analog input 2(1) AIN3 — 7 Analog input Analog input 3(1) GND 3 3 Supply Ground NC 2, 6, 7 2 — No connect; always leave floating SCL 10 10 Digital input Serial clock input. Connect to VDD using a pullup resistor. SDA 9 9 Digital I/O Serial data input and output. Connect to VDD using a pullup resistor. VDD 8 8 Supply Power supply. Connect a 0.1-µF, power-supply decoupling capacitor to GND. |
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