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SN74AUP1G06DPW Fiches technique(PDF) 10 Page - Texas Instruments

No de pièce SN74AUP1G06DPW
Description  Low-Power Single Inverter With Open-Drain Outputs
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
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SN74AUP1G06
SCES590E – JULY 2004 – REVISED OCTOBER 2017
www.ti.com
Product Folder Links: SN74AUP1G06
Submit Documentation Feedback
Copyright © 2004–2017, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The output of this single inverter buffer/driver is open drain, and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs
when the device is powered down. This inhibits current backflow into the device which prevents damage to the
device.
8.2 Functional Block Diagram
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 CMOS Open-Drain Outputs
The open-drain output allows the device to sink current to GND but not to source current from VCC. When the
output is not actively pulling the line low, it will go into a high impedance state (3-state). This allows the device to
be used for a wide variety of applications, including up-translation and down-translation, as the output voltage
can be determined by an external pullup.
The drive capability of this device creates fast edges into light loads so routing and load conditions should be
considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than
the device can sustain without being damaged. It is important for the power output of the device to be limited to
avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the
Absolute Maximum Ratings must be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.


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