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AD9216-80PCB Fiches technique(PDF) 10 Page - Analog Devices |
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AD9216-80PCB Fiches technique(HTML) 10 Page - Analog Devices |
10 / 41 page AD9216 Rev. A | Page 9 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AGND VIN+_A VIN–_A AGND AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B AVDD AGND VIN–_B VIN+_B AGND D2_A D1_A D0_A (LSB) DNC DNC DNC DNC DRVDD DRGND DNC D9_B (MSB) D8_B D7_B D6_B D5_B D4_B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9216 TOP VIEW (Not to Scale) DNC = DO NOT CONNECT Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1, 4, 13, 16 AGND1 Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Duty Cycle Stabilizer (DCS) Mode Pin (Active High). 20 DFS Data Output Format Select Pin. Low for offset binary; high for twos complement. 21 PDWN_B Power-Down Function Selection for Channel B. Logic 0 enables Channel B. Logic 1 powers down Channel B. (Outputs static, not High-Z.) 22 OEB_B Output Enable for Channel B. Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z. 23 to 26, 39, 42 to 45, 58 DNC Do Not Connect Pins. Should be left floating. 27, 30 to 38 D0_B (LSB) to D9_B (MSB) Channel B Data Output Bits. 28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF. |
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