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AD6652BC Fiches technique(PDF) 2 Page - Analog Devices |
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AD6652BC Fiches technique(HTML) 2 Page - Analog Devices |
2 / 76 page AD6652 Rev. 0 | Page 2 of 76 TABLE OF CONTENTS Product Description ......................................................................... 4 Product Highlights ....................................................................... 4 Specifications..................................................................................... 5 Recommended Operating Conditions ...................................... 5 ADC DC Specifications............................................................... 5 ADC Switching Specifications.................................................... 5 ADC AC Specifications ............................................................... 6 Electrical Characteristics ............................................................. 7 General Timing Characteristics ................................................. 8 Microprocessor Port Timing Characteristics ........................... 9 Absolute Maximum Ratings.......................................................... 10 Thermal Characteristics ............................................................ 10 Test Level ..................................................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 14 DDC Timing Diagrams ................................................................. 17 Terminology .................................................................................... 23 ADC Equivalent Circuits........................................................... 23 Theory of Operation ...................................................................... 24 ADC Architecture ...................................................................... 24 Digital Downconverter Architecture Overview ......................... 29 Data Input Matrix....................................................................... 29 Numerically Controlled Oscillator........................................... 29 Second-Order rCIC Filter ......................................................... 29 Fifth-Order CIC Filter ............................................................... 29 RAM Coefficient Filter .............................................................. 29 Interpolating Half-Band Filters and AGC............................... 29 Control Register and Memory Map Address Notation ............. 31 DDC Input Matrix...................................................................... 31 DDC Data Latency ..................................................................... 31 Gain Switching............................................................................ 31 Numerically Controlled Oscillator............................................... 33 Frequency Translation to Baseband......................................... 33 NCO Shadow Register ............................................................... 33 NCO Frequency Hold-Off Register......................................... 33 Phase Offset................................................................................. 33 NCO Control Register ............................................................... 33 Second-Order rCIC Filter ............................................................. 35 rCIC2 Scale Factor ..................................................................... 35 rCIC2 Output Level ................................................................... 36 rCIC2 Rejection.......................................................................... 36 Decimation and Interpolation Registers ................................. 36 rCIC2 Scale Register .................................................................. 36 Fifth-Order CIC Filter ................................................................... 37 CIC5 Rejection ........................................................................... 37 RAM Coefficient Filter .................................................................. 38 RCF Decimation Register.......................................................... 38 RCF Decimation Phase.............................................................. 38 RCF Filter Length....................................................................... 38 RCF Output Scale Factor and Control Register ..................... 39 Interpolating Half-Band Filters .................................................... 40 Automatic Gain Control................................................................ 41 AGC Loop ................................................................................... 41 Desired Signal Level Mode........................................................ 41 Synchronization.......................................................................... 44 User-Configurable Built-In Self-Test (BIST) .............................. 45 RAM BIST ................................................................................... 45 Channel BIST.............................................................................. 45 Channel/Chip Synchronization.................................................... 46 Start .............................................................................................. 46 Hop............................................................................................... 48 |
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