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54283 Datasheet(Fiches technique) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numéro de pièce 54283
Description  4-Bit Binary Full Adder (with Fast Carry)
Télécharger  6 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
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Switching Characteristics
VCC ea50V TA ea25 C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
CL e 15 pF RL e 400X
Units
Min
Max
tPLH
Propagation Delay
21
ns
tPHL
C0 or Sn
21
tPLH
Propagation Delay
24
ns
tPHL
An or Bn to Sn
24
tPLH
Propagation Delay
14
ns
tPHL
C0 to C4
16
tPLH
Propagation Delay
14
ns
tPHL
An or Bn to C4
16
Functional Description
The ’283 adds two 4-bit binary words (A plus B) plus the
incoming carry C0 The binary sum appears on the Sum
(S0 – S3) and outgoing carry (C4 outputs The binary weight
of the various inputs and outputs is indicated by the sub-
script numbers representing powers of two
20 (A0 a B0 a C0) a 21 (A1 a B1) a 22 (A2 a B2) a
23 (A3 a B3) e S0 a 2S1 a 4S2 a 8S3 a 16C4
Where (a) e plus
Interchanging inputs of equal weight does not affect the op-
eration Thus C0 A0 B0 can be arbitrarily assigned to pins
5 6 and 7 Due to the symmetry of the binary add function
the ’283 can be used either with all inputs and outputs ac-
tive HIGH (positive logic) or with all inputs and outputs ac-
tive LOW (negative logic) Note that if C0 is not used it must
be tied LOW for active HIGH logic or tied HIGH for active
LOW logic
Example
C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4
Logic Levels L
LHLH H L
L H H H LL H
Active HIGH 0
0101
1001 1100 1
Active LOW 1
1010
0110 0011 0
Active HIGH 0 a 10 a 9 e 3 a 16
Active LOW 1 a 5 a 6 e 12 a 0
Due to pin limitations the intermediate carries of the ’283
are not brought out for use as inputs or outputs However
other means can be used to effectively insert a carry into or
bring a carry out from an intermediate stage
Figure a
shows a way of making a 3-bit adder Tying the operand
inputs of the fourth adder (A3 B3) LOW makes S3 depen-
dent ony on and equal to the carry from the third adder
Using somewhat the same principle
Figure b shows a way
of dividing the ’283 into a 2-bit and a 1-bit adder The third
stage adder (A2 B2 S2) is used merely as a means of
getting a carry (C10) signal into the fourth stage (via A2 and
B2) and bringing out the carry from the second stage on S2
Note that as long as A2 and B2 are the same whether
HIGH or LOW they do not infuence S2 Similarly when A2
and B2 are the same the carry into the third stage does not
influence they carry out of the third stage
Figure c shows a
method of implementing a 5-input encoder where the inputs
are equally weighted The outputs S0 S1 and S2 present a
binary number equal to the number of inputs I1 – I5 that are
true
Figure d shows one method of implementing a 5-input
majority gate When three or more of the inputs I1 – I5 are
true the output M5 is true
TLF9786 – 3
FIGURE a 3-Bit Adder
TLF9786 – 4
FIGURE b 2-Bit and 1-Bit Adders
3




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