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SL1466 Fiches technique(PDF) 11 Page - Zarlink Semiconductor Inc

No de pièce SL1466
Description  Wideband PLL FM Demodulator
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Fabricant  ZARLINK [Zarlink Semiconductor Inc]
Site Internet  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

SL1466 Fiches technique(HTML) 11 Page - Zarlink Semiconductor Inc

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10
SL1466
Adjust the tank coil by squeezing it slightly until the signal
on both Pins goes high (i.e. > Vcc –0.4 Volts).
These Pins remain high provided the LO frequency is tuned
to within the AFC WINDOW aperture,(
± 0.22MHz).
Optimising the loop components
The network connected from Pin 26 (VIDEO+) to Pin 24
(VIDEOFB–) and from Pin 25 (VIDEO–) to Pin 27 (VIDEO
FB+) forms the loop filter.
The components shown are based on a natural frequency
ƒn of 2.46MHz (
ω
n
=2x
π x2.46 Mrads/s ) and damping factor
ξ =2.6, and assuming Ko = 54MHz/V.
The closed loop gain of the receiver (i.e. the ratio of the
output amplitude to the input carrier frequency variation
versus frequency) has a low pass filter characteristic. Its roll off
is determined by the natural frequency whilst its in band
flatness is determined by the damping factor. Both factors will
affect the 3dB bandwidth as discussed earlier. A narrow
bandwidth will cause loss of high frequency resolution whilst
a large bandwidth will degrade the overall signal/noise in the
output waveform. Thus a selection procedure might be as
follows:
I Calculate R7 (R9) and C9 (C14) based on ƒ n = 2.46MHz,
ξ =2.6 and connect as in Fig. 5.
I Set the video generator for 1Vp–p composite video and the
test generator for a carrier frequency of 479.5MHz, frequency
deviation of 13.5MHz and power level –30dBm.
I Turn on the pre–emphasis filter. Use the 15kHz test pattern
to give black/white screen.
I Monitor the video analyser or TV set.
I Adjust the de–emphasis filter until the bar amplitude is
1Vp–p or 0% error. Reduce transmitter power level until
sparklies or streaking appear.
I Adjust component values for minimum power level when
streaking and sparklies occur together.
AGC settings
The signal level at the input to the limiter preceding the
phase detector is maintained at an level of around –20dBm or
more by an internal (device) AGC and an external (tuner) AGC
circuit.
Current pulses at the carrier frequency with mark/space
proportional to this input power are sourced out of pin 18 (AGC
TIME CONSTANT). These are smoothed and turned into a
voltage by the external components R4, C4. The time constant
R4 C4 should be adjusted so that the expected signal fading
rate can be tracked but its value is not critical, 5mSec typically.
Fig. 4 shows a typical external AGC control curve. Also
shown is the AGCTIMECONST voltage which is an indication
of the level of internal AGC gain being applied, (the control
range is the flat part of the curve).
APPLICATION NOTES
Tuning procedure
The component values shown in the applications circuit
Fig. 6 are optimised for operation at an IF of 479.5MHz. The
AFC circuit can be used to fine tune the external tank as
follows:
With the SL1466 connected as in the test set up Fig. 11 or
its equivalent using 75
Ω cables. Set the video generator for 1V
p-p output. Set the satellite test transmitter for a carrier
frequency of 479.5MHz, frequency deviation 13.5MHz, power
level -30dBm. Turn on the pre-emphasis filter.
Monitor the voltage levels on Pin 2 (DIGFLO) and Pin 3
(DIGFHI).


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