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AD4020BRMZ-RL7 Fiches technique(PDF) 10 Page - Analog Devices |
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AD4020BRMZ-RL7 Fiches technique(HTML) 10 Page - Analog Devices |
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10 / 37 page  Data Sheet AD4020 Rev. A | Page 9 of 36 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 VDD 2 IN+ 3 IN– 4 GND 5 VIO 10 SDI 9 SCK 8 SDO 7 CNV 6 AD4020 TOP VIEW (Not to Scale) Figure 3. 10-Lead MSOP Pin Configuration 1 REF 2 VDD 3 IN+ 4 IN– 5 GND 10 VIO 9 SDI 8 SCK 7 SDO 6 CNV AD4020 TOP VIEW (Not to Scale) NOTES 1. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SPECIFIED PERFORMANCE. Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 REF AI Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 µF X7R ceramic capacitor. 2 VDD P 1.8 V Power Supply. The range of VDD is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 20 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of SCK. 10 VIO P Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. N/A2 EPAD P Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet the specified performance. 1 AI is analog input, P is power, DI is digital input, and DO is digital output. 2 N/A means not applicable. |
Numéro de pièce similaire - AD4020BRMZ-RL7 |
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Description similaire - AD4020BRMZ-RL7 |
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