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STC62WV256DI Fiches technique(PDF) 2 Page - List of Unclassifed Manufacturers

No de pièce STC62WV256DI
Description  VERY LOW POWER/VOLTAGE CMOS SRAM
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STC62WV256DI Fiches technique(HTML) 2 Page - List of Unclassifed Manufacturers

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Revision 2.3
Jan.
2004
2
STC
CIN
Input
Capacitance
VIN=0V
6
pF
CDQ
Input/Output
Capacitance
VI/O=0V
8
pF
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
SYMBOL
PARAMETER
RATING
UNITS
VTERM
Terminal
Voltage
with
Respect to GND
-0.5 to
Vcc+0.5
V
TBIAS
Temperature Under Bias
-40 to +125
O C
TSTG
Storage Temperature
-60 to +150
O C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
STC62WV256
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70 O C2.4V ~ 5.5V
Industrial
-40 O C to +85 O C2.4V ~ 5.5V
R0201-
STC62WV256
Name
Function
A0-A14 Address Input
These 15 address inputs select one of the 32768 x 8-bit words in the RAM
CE Chip Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. If chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0 – DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
PIN DESCRIPTIONS
MODE
WE
CE
OE
I/O OPERATION
Vcc CURRENT
Not selected
X
H
X
High Z
I
CCSB, ICCSB1
Output Disabled
H
L
H
High Z
I
CC
Read
H
L
L
DOUT
I
CC
Write
L
L
X
DIN
I
CC
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT


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